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    Metallization levels and methods of making thereof
    2.
    发明授权
    Metallization levels and methods of making thereof 有权

    公开(公告)号：US10134580B1

    公开(公告)日：2018-11-20

    申请号：US15677693

    申请日：2017-08-15

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Nicholas V. LiCausi ,  Errol Todd Ryan ,  Sean Xuan Lin

    IPC: H01L21/02 ,  H01L21/48 ,  H01L21/3213 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532

    Abstract: Structures for metallization levels of integrated circuits and associated fabrication methods. A first metallization level with a metallization line is formed. A second metallization level is formed over the first metallization level, having two metallization lines and two conductive vias extending from the two metallization lines to the metallization line in the first metallization level. The first metallization line is separated into a first section and a second section disconnected from the first section, so that the first section is connected by one conductive via to one metallization line in the second metallization level, and the second section is connected by the other conductive via to the other metallization line in the second level.

    Semiconductor device having a self-forming barrier layer at via bottom
    3.
    发明授权
    Semiconductor device having a self-forming barrier layer at via bottom 有权
    半导体器件在通孔底部具有自形成阻挡层

    公开(公告)号：US08907483B2

    公开(公告)日：2014-12-09

    申请号：US13648433

    申请日：2012-10-10

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Larry Zhao ,  Ming He ,  Xunyuan Zhang ,  Sean Xuan Lin

    IPC: H01L23/48

    CPC classification number: H01L23/5226 ,  H01L21/76831 ,  H01L21/76846 ,  H01L21/76855 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An approach for forming a semiconductor device is provided. In general, the device is formed by providing a metal layer, a cap layer over the metal layer, and an ultra low k layer over the cap layer. A via is then formed through the ultra low k layer and the cap layer. Once the via is formed, a barrier layer (e.g., cobalt (Co), tantalum (Ta), cobalt-tungsten-phosphide (CoWP), or other metal capable of acting as a copper (CU) diffusion barrier) is selectively applied to a bottom surface of the via. A liner layer (e.g., manganese (MN) or aluminum (AL)) is then applied to a set of sidewalls of the via. The via may then be filled with a subsequent metal layer (with or without a seed layer), and the device may the then be further processed (e.g., annealed).

    Abstract translation: 提供了一种用于形成半导体器件的方法。 通常，通过在金属层上设置金属层，覆盖层和覆盖层上的超低k层来形成器件。 然后通过超低k层和盖层形成通孔。 一旦形成通孔，就可以选择性地将阻挡层（例如钴（Co），钽（Ta），钴 - 钨 - 磷化物（CoWP）或其它能够用作铜（CU）扩散阻挡层的金属） 通孔的底面。 然后将衬垫层（例如锰（MN）或铝（AL））施加到通孔的一组侧壁。 然后可以用随后的金属层（具有或不具有种子层）填充通孔，然后可以进一步处理（例如，退火）该器件。

    Metal interconnects for super (skip) via integration
    5.
    发明授权
    Metal interconnects for super (skip) via integration 有权

    公开(公告)号：US10026687B1

    公开(公告)日：2018-07-17

    申请号：US15437100

    申请日：2017-02-20

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Sean Xuan Lin ,  Xunyuan Zhang ,  Shao Beng Law ,  James Jay McMahon

    IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to metal interconnect structures for super (skip) via integration and methods of manufacture. The structure includes: a first wiring layer with one or more wiring structures; a second wiring layer including an interconnect and wiring structure; and at least one upper wiring layer with one or more via interconnect and wiring structures located above the second wiring layer. The one or more via interconnect and wiring structures partially including a first metal material and remaining portions with a conductive material over the first metal material. A skip via passes through the second wiring layer and extends to the one or more wiring structures of the first wiring layer. The skip via partially includes the metal material and remaining portions of the skip via includes the conductive material over the first metal material.

    Semiconductor device having a self-forming barrier layer at via bottom
    8.
    再颁专利
    Semiconductor device having a self-forming barrier layer at via bottom 有权

    公开(公告)号：USRE47630E1

    公开(公告)日：2019-10-01

    申请号：US15335313

    申请日：2016-10-26

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Larry Zhao ,  Ming He ,  Xunyuan Zhang ,  Sean Xuan Lin

    IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L23/48

    Abstract: An approach for forming a semiconductor device is provided. In general, the device is formed by providing a metal layer, a cap layer over the metal layer, and an ultra low k layer over the cap layer. A via is then formed through the ultra low k layer and the cap layer. Once the via is formed, a barrier layer (e.g., cobalt (Co), tantalum (Ta), cobalt-tungsten-phosphide (CoWP), or other metal capable of acting as a copper (CU) diffusion barrier) is selectively applied to a bottom surface of the via. A liner layer (e.g., manganese (MN) or aluminum (AL)) is then applied to a set of sidewalls of the via. The via may then be filled with a subsequent metal layer (with or without a seed layer), and the device may the then be further processed (e.g., annealed).

    Methods of using a metal protection layer to form replacement gate structures for semiconductor devices
    10.
    发明授权
    Methods of using a metal protection layer to form replacement gate structures for semiconductor devices 有权
    使用金属保护层形成用于半导体器件的替代栅极结构的方法

    公开(公告)号：US09425103B2

    公开(公告)日：2016-08-23

    申请号：US14560102

    申请日：2014-12-04

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  Chanro Park ,  Sean Xuan Lin

    IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/51 ,  H01L29/423 ,  H01L29/49 ,  H01L27/088

    CPC classification number: H01L21/823468 ,  H01L21/02181 ,  H01L21/28088 ,  H01L21/32133 ,  H01L21/823456 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628

    Abstract: A method that involves forming a high-k gate insulation layer, a work-function adjusting metal layer and a metal protection layer in first and second replacement gate cavities, wherein the metal protection layer is formed so as to pinch-off the first gate cavity while leaving the second gate cavity partially un-filled, forming a first bulk conductive metal layer in the un-filled portion of the second gate cavity, removing substantially all of the metal protection layer in the first gate cavity while leaving a portion of the metal protection layer in the second gate cavity, forming a second conductive metal layer within the first and second replacement gate cavities, recessing the conductive metal layers so as to define first and second gate-cap cavities in the first and second replacement gate cavities, respectively, and forming gate cap layers within the first and second gate-cap cavities.

    Abstract translation: 一种涉及在第一和第二替换栅腔中形成高k栅极绝缘层，功函数调整金属层和金属保护层的方法，其中金属保护层形成为夹住第一栅极腔 同时使第二栅极腔部分未填充，在第二栅极腔的未填充部分中形成第一体导电金属层，基本上除去第一栅极腔中的所有金属保护层，同时留下金属的一部分 在所述第二栅极腔中形成保护层，在所述第一和第二替代栅极腔内形成第二导电金属层，使所述导电金属层凹陷，以分别在所述第一和第二替换栅极腔中限定第一和第二栅极盖腔， 以及在所述第一和第二栅极盖腔内形成栅极盖层。

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