公开(公告)号：US09570397B1

公开(公告)日：2017-02-14

申请号：US14964786

申请日：2015-12-10

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Su Chen Fan ,  Vimal Kamineni ,  Andre P. Labonte ,  Ruilong Xie

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76805 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76879 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/53295 ,  H01L23/535

Abstract: A local interconnect structure includes a substrate having a dielectric layer and at least one semiconductor contact structure embedded in the dielectric layer. An electrically conductive material is deposited in a non-eroded contact trench that defines at least one electrically conducive contact via. The contact via extends from a first end that is flush with an upper surface of the dielectric layer to a second end that contacts the at one semiconductor contact structure. A local conductive material layer is formed in the dielectric layer and contacts the first end of the contact via. The non-eroded contact trench includes sharp upper corners formed at approximately ninety degrees with respect to the first end of the contact via.

Abstract translation: 局部互连结构包括具有电介质层和嵌入电介质层中的至少一个半导体接触结构的衬底。 导电材料沉积在限定至少一个导电接触通孔的非侵蚀接触沟槽中。 接触通孔从与电介质层的上表面齐平的第一端延伸到接触一个半导体接触结构的第二端。 在电介质层中形成局部导电材料层并接触接触通孔的第一端。 非侵蚀接触沟槽包括相对于接触通孔的第一端大致九十度形成的尖锐的上角。

公开(公告)号：US09362377B1

公开(公告)日：2016-06-07

申请号：US14633998

申请日：2015-02-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hoon Kim ,  Vimal Kamineni ,  Min Gyu Sung ,  Chanro Park

IPC: H01L21/44 ,  H01L23/52 ,  H01L29/49 ,  H01L21/28 ,  H01L21/285 ,  H01L21/321 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/321 ,  H01L21/32134 ,  H01L29/42376 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: Methods for forming a semiconductor gate electrode with a reflowed Co layer and the resulting device are disclosed. Embodiments include forming a trench in an ILD on a substrate; forming a high-k dielectric layer, a WF layer, and a Co layer sequentially on sidewall and bottom surfaces of the trench; reflowing a portion of the Co layer from the WF layer on the sidewall surfaces of the trench to the WF layer on the bottom surface of the trench; removing a remainder of the Co layer from the WF layer on the sidewall surfaces of the trench, above an upper surface of the reflowed Co; recessing the WF layer to the upper surface of the reflowed Co layer, forming a cavity above the reflowed Co layer; and filling the cavity with metal to form a gate electrode.

Abstract translation: 公开了用于形成具有回流Co层的半导体栅电极的方法和所得到的器件。 实施例包括在衬底上形成ILD中的沟槽; 在沟槽的侧壁和底表面上依次形成高k电介质层，WF层和Co层; 将Co层的一部分从沟槽的侧壁表面上的WF层回流到沟槽的底表面上的WF层; 从所述沟槽的侧壁表面上的所述WF层中除去所述Co层的剩余部分，在所述回流Co的上表面上方; 将WF层凹陷到回流Co层的上表面，在回流Co层上方形成空腔; 并用金属填充空腔以形成栅电极。

公开(公告)号：US20160049370A1

公开(公告)日：2016-02-18

申请号：US14457370

申请日：2014-08-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vimal Kamineni ,  Xiuyu Cai ,  Xunyuan Zhang

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76831 ,  H01L21/285 ,  H01L23/485 ,  H01L23/53266 ,  H01L23/53271 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One method disclosed herein includes, among other things, forming at least one layer of insulating material above a semiconductor layer, performing at least one contact opening etching process to form a contact opening in the at least one layer of insulating material that exposes a portion of the semiconductor layer, selectively depositing a metal-oxide insulating material through the contact opening on the exposed surface of the semiconductor layer, and forming a conductive contact in the contact opening that contacts the metal-oxide insulating material.

Abstract translation: 本文公开的一种方法包括在半导体层之上形成至少一层绝缘材料，执行至少一个接触开口蚀刻工艺，以在所述至少一层绝缘材料中形成接触开口，该绝缘材料层暴露一部分 半导体层，通过半导体层的暴露表面上的接触开口选择性地沉积金属氧化物绝缘材料，并且在与金属氧化物绝缘材料接触的接触开口中形成导电接触。

公开(公告)号：US20160049332A1

公开(公告)日：2016-02-18

申请号：US14457708

申请日：2014-08-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Vimal Kamineni ,  William J. Taylor, JR.

IPC: H01L21/768 ,  H01L23/535

CPC classification number: H01L29/4975 ,  H01L21/28525 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/76889 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/535 ,  H01L29/41758 ,  H01L29/78 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One method disclosed herein includes, among other things, a method of forming a contact structure to a source/drain region of a transistor device. The transistor device includes a gate structure and a gate cap layer positioned above the gate structure. The method includes forming an extended-height epi contact structure that is conductively coupled to the source/drain region. The extended-height epi contact structure includes an upper surface that is positioned at a height level that is above a height level of an upper surface of the gate cap layer. The method further includes performing an etching process to trim at least a lateral width of a portion of the extended-height epi contact structure, and, after performing the etching process, forming a metal silicide material on at least a portion of the trimmed extended-height epi contact structure and forming a conductive contact on the metal silicide material.

Abstract translation: 本文公开的一种方法包括形成与晶体管器件的源极/漏极区域的接触结构的方法。 晶体管器件包括栅极结构和位于栅极结构上方的栅极帽层。 该方法包括形成导电耦合到源极/漏极区的扩展高度外延接触结构。 所述延伸高度外延接触结构包括位于所述栅极盖层的上表面的高度以上的高度水平处的上表面。 该方法还包括执行蚀刻工艺以修剪延伸高度外延接触结构的一部分的至少横向宽度，并且在执行蚀刻工艺之后，在修剪的延伸高度外延接触结构的至少一部分上形成金属硅化物材料， 高度epi接触结构，并在金属硅化物材料上形成导电接触。