公开(公告)号：US10485111B2

公开(公告)日：2019-11-19

申请号：US15647400

申请日：2017-07-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shao Beng Law ,  Nicholas V. LiCausi ,  Errol Todd Ryan ,  James McMahon ,  Ryan S. Smith ,  Xunyuan Zhang

IPC: H05K3/46 ,  H05K3/40 ,  H05K1/11 ,  H01L21/768

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to via and skip via structures and methods of manufacture. The method includes: forming a first metallization layer with a first capping layer over the first metallization layer; forming a second metallization layer with a second capping layer over the second metallization layer; forming a partial skip via structure to the first metallization layer by removing a portion of the first capping layer and the second capping and depositing conductive material in an opening formed in the second metallization layer; forming a third capping layer over the filled partial skip via and the second capping layer; and forming a remaining portion of a skip via structure in alignment with the partial skip via structure by opening the third capping layer to expose the conductive material of the partial skip via.

公开(公告)号：US10304833B1

公开(公告)日：2019-05-28

申请号：US15898812

申请日：2018-02-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Puneet Harischandra Suvarna ,  Bipul C. Paul ,  Ruilong Xie ,  Bartlomiej Jan Pawlak ,  Lars W. Liebmann ,  Daniel Chanemougame ,  Nicholas V. LiCausi ,  Andreas Knorr

IPC: H01L29/775 ,  H01L29/78 ,  H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L27/12

Abstract: A device includes a first nano-sheet of a first semiconductor material. First source/drain regions are positioned adjacent ends of the first nano-sheet. A first dielectric material is positioned above the first source/drain regions. A second nano-sheet of a second semiconductor material is positioned above the first nano-sheet. Second source/drain regions are positioned adjacent ends of the second nano-sheet and above the first dielectric material. A gate structure has a first portion capacitively coupled to the first nano-sheet and a second portion capacitively coupled to the second nano-sheet. A first source/drain contact contacts a first portion of the second source/drain regions in a first region where the first and second source/drain regions do not vertically overlap. The first source/drain contact has a first depth that extends below a height of an upper surface of the first source/drain regions in a second region where the first and second source/drain regions vertically overlap.

公开(公告)号：US20190088500A1

公开(公告)日：2019-03-21

申请号：US15705956

申请日：2017-09-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sean Xuan Lin ,  Xunyuan Zhang ,  Mark V. Raymond ,  Errol Todd Ryan ,  Nicholas V. LiCausi

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/532

Abstract: Methods of forming interconnects. An interconnect opening is formed in a dielectric layer. A first conductor layer composed of a first metal is formed in the interconnect opening. A second conductor layer is formed inside the interconnect opening by displacing the first metal of the first conductor layer and replacing the first metal with a second metal different from the first metal.

公开(公告)号：US20190027401A1

公开(公告)日：2019-01-24

申请号：US15653638

申请日：2017-07-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： James McMahon ,  Ryan S. Smith ,  Nicholas V. LiCausi ,  Errol Todd Ryan ,  Xunyuan Zhang ,  Shao Beng Law

IPC: H01L21/768 ,  H01L23/522

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to dielectric repair for via and skip via structures and methods of manufacture. The method includes: etching a via structure in a dielectric layer; repairing sidewalls of the via structure with a repair agent; and extending the via structure with an additional etching into a lower dielectric layer to form a skip via structure exposing a metallization layer.

公开(公告)号：US20190013240A1

公开(公告)日：2019-01-10

申请号：US15643843

申请日：2017-07-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nicholas V. LiCausi ,  Xunyuan Zhang ,  Errol Todd Ryan

IPC: H01L21/768 ,  H01L21/3215 ,  H01L21/3213 ,  H01L23/532 ,  H01L23/522

Abstract: Interconnects and methods for forming interconnects. An interconnect opening is formed in a dielectric layer, and a conductive layer is formed in the interconnect opening. A modified section is formed in the conductive layer near a top surface of the conductive layer. After the modified section is formed, the modified section of the conductive layer is recessed with an etching process that at least partially removes the modified section. The modified section may have a composition that includes niobium.

公开(公告)号：US10134580B1

公开(公告)日：2018-11-20

申请号：US15677693

申请日：2017-08-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nicholas V. LiCausi ,  Errol Todd Ryan ,  Sean Xuan Lin

IPC: H01L21/02 ,  H01L21/48 ,  H01L21/3213 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: Structures for metallization levels of integrated circuits and associated fabrication methods. A first metallization level with a metallization line is formed. A second metallization level is formed over the first metallization level, having two metallization lines and two conductive vias extending from the two metallization lines to the metallization line in the first metallization level. The first metallization line is separated into a first section and a second section disconnected from the first section, so that the first section is connected by one conductive via to one metallization line in the second metallization level, and the second section is connected by the other conductive via to the other metallization line in the second level.

公开(公告)号：US08846491B1

公开(公告)日：2014-09-30

申请号：US13921377

申请日：2013-06-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Daniel Pham ,  Zhenyu Hu ,  Andy Wei ,  Nicholas V. LiCausi

IPC: H01L21/76 ,  H01L29/78 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L29/785 ,  H01L21/02104 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795

Abstract: Embodiments herein provide approaches for forming a diffusion break during a replacement metal gate process. Specifically, a semiconductor device is provided with a set of replacement metal gate (RMG) structures over a set of fins patterned from a substrate; a dielectric material over an epitaxial junction area; an opening formed between the set of RMG structures and through the set of fins, wherein the opening extends through the dielectric material, the expitaxial junction area, and into the substrate; and silicon nitride (SiN) deposited within the opening to form the diffusion break.

Abstract translation: 本文的实施例提供了在替换金属浇口工艺期间形成扩散断裂的方法。 具体而言，半导体器件在从衬底图案化的一组鳍片上设置有一组置换金属栅极（RMG）结构; 在外延结区上的电介质材料; 所述开口形成在所述一组RMG结构之间并且穿过所述一组翅片，其中所述开口延伸穿过所述电介质材料，所述外延结结区域并进入所述基板; 和沉积在开口内的氮化硅（SiN）以形成扩散断裂。

公开(公告)号：US08691640B1

公开(公告)日：2014-04-08

申请号：US13745927

申请日：2013-01-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nicholas V. LiCausi ,  Jeremy A. Wahl

IPC: H01L21/00

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: One illustrative method disclosed herein includes forming a plurality of trenches in a semiconductor substrate to thereby define an initial fin structure, forming sidewall spacers adjacent the initial fin structure, wherein the spacers cover a first portion of the initial fin structure and expose a second a portion of the initial fin structure, performing a doping process to form N-type doped regions in at least the exposed portion of the initial fin structure, and performing an etching process to remove at least a portion of the doped regions and thereby define a final fin structure that is vertically spaced apart from the substrate.

Abstract translation: 本文公开的一种示例性方法包括在半导体衬底中形成多个沟槽，从而限定初始鳍结构，形成邻近初始鳍结构的侧壁间隔物，其中间隔物覆盖初始鳍结构的第一部分并暴露第二部分 的初始鳍结构，执行掺杂工艺以在至少初始鳍结构的暴露部分中形成N型掺杂区，并且执行蚀刻工艺以去除至少一部分掺杂区域，从而限定最终鳍 与衬底垂直间隔开的结构。