中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

79 records (took 0.025 seconds)

    LATERAL BIPOLAR TRANSISTOR STRUCTURE WITH INNER AND OUTER SPACERS AND METHODS TO FORM SAME
    32.
    发明申请
    LATERAL BIPOLAR TRANSISTOR STRUCTURE WITH INNER AND OUTER SPACERS AND METHODS TO FORM SAME 有权

    公开(公告)号：US20230083044A1

    公开(公告)日：2023-03-16

    申请号：US17457325

    申请日：2021-12-02

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Alexander M. Derrickson ,  John L. Lemon ,  Haiting Wang ,  Judson R. Holt

    IPC: H01L29/735 ,  H01L29/10 ,  H01L29/66

    Abstract: Embodiments of the disclosure provide a lateral bipolar transistor structure with inner and outer spacers, and related methods. A lateral bipolar transistor structure may have an emitter/collector (E/C) layer over an insulator. The E/C layer has a first doping type. A first base layer is on the insulator and adjacent the E/C layer. The first base layer has a second doping type opposite the first doping type. A second base layer is on the first base layer and having the second doping type. A dopant concentration of the second base layer is greater than a dopant concentration of the first base layer. An inner spacer is on the E/C layer and adjacent the second base layer. An outer spacer is on the E/C layer and adjacent the inner spacer.

    LATERAL BIPOLAR TRANSISTOR STRUCTURE WITH BASE LAYER OF VARYING HORIZONTAL WIDTH AND METHODS TO FORM SAME
    33.
    发明申请
    LATERAL BIPOLAR TRANSISTOR STRUCTURE WITH BASE LAYER OF VARYING HORIZONTAL WIDTH AND METHODS TO FORM SAME 有权

    公开(公告)号：US20230067523A1

    公开(公告)日：2023-03-02

    申请号：US17456943

    申请日：2021-11-30

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Haiting Wang ,  Hong Yu ,  Zhenyu Hu ,  Alexander M. Derrickson

    IPC: H01L29/10 ,  H01L29/735 ,  H01L29/66

    Abstract: Embodiments of the disclosure provide a lateral bipolar transistor with a base layer of varying horizontal thickness, and related methods to form the same. A lateral bipolar transistor may include an emitter/collector (E/C) layer on a semiconductor layer. A first base layer is on the semiconductor layer and horizontally adjacent the E/C layer. The first base layer has a lower portion having a first horizontal width from the E/C layer. The first base layer also has an upper portion on the lower portion, with a second horizontal width from the E/C layer greater than the first horizontal width. A second base layer is on the first base layer and adjacent a spacer. The upper portion of the first base layer separates a lower surface of the second base layer from the E/C layer.

    Transistor comprising an air gap positioned adjacent a gate electrode
    34.
    发明授权
    Transistor comprising an air gap positioned adjacent a gate electrode 有权

    公开(公告)号：US11456382B2

    公开(公告)日：2022-09-27

    申请号：US16664056

    申请日：2019-10-25

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Laertis Economikos ,  Shesh Mani Pandey ,  Hui Zang ,  Haiting Wang ,  Jinping Liu

    IPC: H01L29/49 ,  H01L29/423 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66

    Abstract: A transistor device disclosed herein includes, among other things, a gate electrode positioned above a semiconductor material region, a sidewall spacer positioned adjacent the gate electrode, a gate insulation layer having a first portion positioned between the gate electrode and the semiconductor material region and a second portion positioned between a lower portion of the sidewall spacer and the gate electrode along a portion of a sidewall of the gate electrode, an air gap cavity located between the sidewall spacer and the gate electrode and above the second portion of the gate insulation layer, and a gate cap layer positioned above the gate electrode, wherein the gate cap layer seals an upper end of the air gap cavity so as to define an air gap positioned adjacent the gate electrode.

    Methods of forming transistor devices comprising a single semiconductor structure and the resulting devices
    35.
    发明授权
    Methods of forming transistor devices comprising a single semiconductor structure and the resulting devices 有权

    公开(公告)号：US11349030B2

    公开(公告)日：2022-05-31

    申请号：US16739299

    申请日：2020-01-10

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Jiehui Shu ,  Haiting Wang ,  Hong Yu

    IPC: H01L29/78 ,  H01L27/088 ,  H01L29/66 ,  H01L21/762 ,  H01L21/02

    Abstract: A transistor device that includes a single semiconductor structure having an outer perimeter and a vertical height, wherein the single semiconductor structure is at least partially defined by a trench formed in a semiconductor substrate and a first layer of material positioned on the bottom surface of the trench and around the outer perimeter of the single semiconductor structure. The device also includes a second layer of material positioned on the first layer of material and around the outer perimeter of the single semiconductor structure, a gap between the outer perimeter of the single semiconductor structure and both the first and second layers of material (when considered collectively) and an insulating sidewall spacer positioned in the gap, wherein the insulating sidewall spacer has a vertical height that is less than the vertical height of the single semiconductor structure.

    Active and dummy fin structures
    36.
    发明授权
    Active and dummy fin structures 有权

    公开(公告)号：US11264504B2

    公开(公告)日：2022-03-01

    申请号：US16751779

    申请日：2020-01-24

    Applicant: GLOBALFOUNDRIES U.S. INC.

    Inventor： Yanping Shen ,  Haiting Wang ,  Hong Yu

    IPC: H01L29/78 ,  H01L29/16 ,  H01L29/423

    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a scheme of active and dummy fin structures and methods of manufacture. The structure includes: an active fin structure; at least one dummy fin structure running along at least one side of the active fin structure along its length; a fin cut separating the at least one dummy fin structure along its longitudinal axes; and a gate structure extending over the active fin structure and the fin cut.

    IC products formed on a substrate having localized regions of high resistivity and methods of making such IC products
    39.
    发明授权
    IC products formed on a substrate having localized regions of high resistivity and methods of making such IC products 有权

    公开(公告)号：US11114466B2

    公开(公告)日：2021-09-07

    申请号：US16774087

    申请日：2020-01-28

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Sipeng Gu ,  Jiehui Shu ,  Haiting Wang

    IPC: H01L27/12 ,  H01L21/762 ,  H01L21/306 ,  H01L21/84 ,  H01L21/265 ,  H01L21/76

    Abstract: One illustrative IC product disclosed herein includes an (SOI) substrate comprising a base semiconductor layer, a buried insulation layer and an active semiconductor layer positioned above the buried insulation layer. In this particular example, the IC product also includes a first region of localized high resistivity formed in the base semiconductor layer, wherein the first region of localized high resistivity has an electrical resistivity that is greater than an electrical resistivity of the material of the base semiconductor layer. The IC product also includes a first region comprising integrated circuits formed above the active semiconductor layer, wherein the first region comprising integrated circuits is positioned vertically above the first region of localized high resistivity in the base semiconductor layer.

Patent Agency Ranking