公开(公告)号：US07101756B2

公开(公告)日：2006-09-05

申请号：US10781987

申请日：2004-02-18

Applicant: Randhir P. S. Thakur ,  Garry A. Mercaldi ,  Michael Nuttall ,  Shenlin Chen ,  Er-Xuan Ping

Inventor： Randhir P. S. Thakur ,  Garry A. Mercaldi ,  Michael Nuttall ,  Shenlin Chen ,  Er-Xuan Ping

IPC: H01L21/8242 ,  H01L21/336 ,  H01L21/20

CPC classification number: G11C11/404 ,  G11C17/16 ,  H01L21/28568 ,  H01L21/76888 ,  H01L27/1085 ,  H01L27/10852 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/60 ,  H01L28/82 ,  H01L28/84

Abstract: Structures and methods for making a semiconductor structure are discussed. The semiconductor structure includes a rough surface having protrusions formed from an undoped silicon film. If the semiconductor structure is a capacitor, the protrusions help to increase the capacitance of the capacitor. The semiconductor structure also includes a relatively smooth surface abutting the rough surface, wherein the relatively smooth surface is formed from a polycrystalline material.

公开(公告)号：US06803280B2

公开(公告)日：2004-10-12

申请号：US10060451

申请日：2002-01-30

Applicant: Michael Nuttall ,  Garry A. Mercaldi

Inventor： Michael Nuttall ,  Garry A. Mercaldi

IPC: H01L21336

CPC classification number: H01L21/28273 ,  H01L29/42324 ,  H01L29/511 ,  Y10S438/954

Abstract: A dielectric insulating composite for insulating a floating gate from a control gate in a non-volatile memory is described. A material, such as an undoped polysilicon, amorphous silicon, or amorphous polysilicon or a silicon rich nitride, is inserted in the gate structure. The oxide film that results from the oxidation of these films is relatively free from impurities. As a result, charge leakage between the floating gate and control gate is reduced.

公开(公告)号：US06791148B2

公开(公告)日：2004-09-14

申请号：US10369786

申请日：2003-02-18

Applicant: Michael Nuttall ,  Garry A. Mercaldi

Inventor： Michael Nuttall ,  Garry A. Mercaldi

IPC: H01L2976

CPC classification number: H01L21/28273 ,  H01L29/42324 ,  H01L29/511 ,  Y10S438/954

Abstract: A dielectric insulating composite for insulating a floating gate from a control gate in a non-volatile memory is described. A material, such as an undoped polysilicon, amorphous silicon, or amorphous polysilicon or a silicon rich nitride, is inserted in the gate structure. The oxide film that results from the oxidation of these films is relatively free from impurities. As a result, charge leakage between the floating gate and control gate is reduced.

Abstract translation: 描述了用于将浮动栅极与非易失性存储器中的控制栅极绝缘的绝缘绝缘复合材料。 诸如未掺杂的多晶硅，非晶硅或无定形多晶硅或富含硅的氮化物的材料插入栅极结构中。 由这些膜的氧化产生的氧化膜相对不含杂质。 结果，浮栅和控制栅之间的电荷泄漏减小。

公开(公告)号：US06746922B2

公开(公告)日：2004-06-08

申请号：US10060613

申请日：2002-01-30

Applicant: Michael Nuttall ,  Garry A. Mercaldi

Inventor： Michael Nuttall ,  Garry A. Mercaldi

IPC: H01L21336

CPC classification number: H01L21/28273 ,  H01L29/42324 ,  H01L29/511 ,  Y10S438/954

Abstract: A dielectric insulating composite for insulating a floating gate from a control gate in a non-volatile memory is described. A material, such as an undoped polysilicon, amorphous silicon, or amorphous polysilicon or a silicon rich nitride, is inserted in the gate structure. The oxide film that results from the oxidation of these films is relatively free from impurities. As a result, charge leakage between the floating gate and control gate is reduced.

公开(公告)号：US06639266B1

公开(公告)日：2003-10-28

申请号：US09651470

申请日：2000-08-30

Applicant: Donald L. Yates ,  Garry A. Mercaldi

Inventor： Donald L. Yates ,  Garry A. Mercaldi

IPC: H01L27108

CPC classification number: H01L28/91 ,  H01L21/31056 ,  H01L27/10855 ,  H01L28/84

Abstract: Container structures for use in integrated circuits and methods of their manufacture without the use of mechanical planarization such as chemical-mechanical planarization (CMP), thus eliminating CMP-induced defects and variations. The methods utilize localized masking of holes for protection of the inside of the holes during non-mechanical removal of exposed surface layers. The localized masking is accomplished through differential exposure of a resist layer to electromagnetic or thermal energy. The methods further include modifying the removal selectivity of the surface material relative to material protected by the localized masking. Modification of the removal selectivity eases or quickens removal of the surface material. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Abstract translation: 用于集成电路的容器结构及其制造方法，而不使用机械平面化（例如化学机械平面化（CMP）），从而消除了CMP引起的缺陷和变化。 该方法利用在非机械去除暴露的表面层期间的孔的局部掩蔽来保护孔的内部。 通过将抗蚀剂层与电磁或热能的差分曝光来实现局部掩蔽。 所述方法还包括改变表面材料相对于通过局部掩蔽保护的材料的去除选择性。 去除选择性的改性缓和或加快了表面材料的去除。 容器结构适用于并入这种存储单元的存储器单元和装置以及其它集成电路。

公开(公告)号：US06573554B2

公开(公告)日：2003-06-03

申请号：US09912151

申请日：2001-07-24

Applicant: Donald L. Yates ,  Garry A. Mercaldi

Inventor： Donald L. Yates ,  Garry A. Mercaldi

IPC: H01L2978

CPC classification number: H01L28/92 ,  G03F7/0035 ,  G03F7/201 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/0275 ,  H01L21/32139 ,  H01L27/10852 ,  H01L28/84 ,  H01L28/91

Abstract: Container structures for use in integrated circuits and methods of their manufacture without the use of mechanical planarization such as chemical-mechanical planarization (CMP), thus eliminating CMP-induced defects and variations. The methods utilize localized masking of holes for protection of the inside of the holes during non-mechanical removal of exposed surface layers. The localized masking is accomplished through differential exposure of a resist layer to electromagnetic or thermal energy. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

公开(公告)号：US06541811B2

公开(公告)日：2003-04-01

申请号：US09681828

申请日：2001-06-12

Applicant: Randhir P. S. Thakur ,  Garry A. Mercaldi ,  Michael Nuttall

Inventor： Randhir P. S. Thakur ,  Garry A. Mercaldi ,  Michael Nuttall

IPC: H01L27108

CPC classification number: H01L27/11502 ,  G11C11/404 ,  G11C17/16 ,  H01L21/28568 ,  H01L21/76888 ,  H01L27/1085 ,  H01L27/11507 ,  H01L28/60 ,  H01L28/84

Abstract: A semiconductor structure includes a dielectric layer having first and second opposing sides. A conductive layer is adjacent to the first side of the dielectric layer and is coupled to a first terminal, and a conductive barrier layer is adjacent to the second side of the dielectric layer and is coupled to a second terminal. The conductive barrier layer may be formed from tungsten nitride, tungsten silicon nitride, titanium silicon nitride or other barrier materials.

公开(公告)号：US06392284B1

公开(公告)日：2002-05-21

申请号：US09353576

申请日：1999-07-15

Applicant: Randhir P. S. Thakur ,  Garry A. Mercaldi ,  Michael Nuttall

Inventor： Randhir P. S. Thakur ,  Garry A. Mercaldi ,  Michael Nuttall

IPC: H01L2900

CPC classification number: G11C11/404 ,  G11C17/16 ,  H01L21/28568 ,  H01L21/76888 ,  H01L27/1085 ,  H01L28/60

Abstract: A semiconductor structure includes a dielectric layer having first and second opposing sides. A conductive layer is adjacent to the first side of the dielectric layer and is coupled to a first terminal, and a conductive barrier layer is adjacent to the second side of the dielectric layer and is coupled to a second terminal. The conductive barrier layer may be formed from tungsten nitride, tungsten silicon nitride, titanium silicon nitride or other barrier materials.

Abstract translation: 半导体结构包括具有第一和第二相对侧的电介质层。 导电层与电介质层的第一侧相邻并且耦合到第一端子，并且导电阻挡层与电介质层的第二侧相邻并耦合到第二端子。 导电阻挡层可以由氮化钨，氮化钨，氮化钛或其它阻挡材料形成。

公开(公告)号：US06316370B1

公开(公告)日：2001-11-13

申请号：US09644699

申请日：2000-08-24

Applicant: Garry A. Mercaldi ,  Donald L. Yates

Inventor： Garry A. Mercaldi ,  Donald L. Yates

IPC: H01L21461

CPC classification number: H01L21/32134

Abstract: The present invention provides an etching composition which includes a polyhydric alcohol in combination with two inorganic acids. Preferably the etching composition of the present invention is a mixture of a glycol, nitric acid and hydrofluoric acid, with propylene glycol being preferred. The etching composition of the present invention achieves a selectivity of greater than 70:1, doped material to undoped material. The present invention provides an etching formulation which has increased selectivity of doped polysilicon to undoped polysilicon and provides an efficient integrated circuit fabrication process without requiring time consuming and costly processing modifications to the etching apparatus or production apparatus.

Abstract translation: 本发明提供一种蚀刻组合物，其包含与两种无机酸组合的多元醇。 优选地，本发明的蚀刻组合物是二醇，硝酸和氢氟酸的混合物，优选丙二醇。 本发明的蚀刻组合物实现大于70:1的掺杂材料对未掺杂材料的选择性。 本发明提供了一种蚀刻配方，其具有增加掺杂多晶硅对未掺杂多晶硅的选择性，并且提供了有效的集成电路制造工艺，而不需要对蚀刻设备或生产设备进行耗时且昂贵的处理修改。

公开(公告)号：US5969983A

公开(公告)日：1999-10-19

申请号：US260994

申请日：1999-03-01

Applicant: Randhir P. S. Thakur ,  Garry A. Mercaldi ,  Michael Nuttall

Inventor： Randhir P. S. Thakur ,  Garry A. Mercaldi ,  Michael Nuttall

IPC: G11C11/404 ,  G11C17/16 ,  H01L21/02 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8242 ,  G11C11/24

CPC classification number: G11C11/404 ,  G11C17/16 ,  H01L21/28568 ,  H01L21/76888 ,  H01L27/1085 ,  H01L28/60

Abstract: A semiconductor structure includes a dielectric layer having first and second opposing sides. A conductive layer is adjacent to the first side of the dielectric layer and is coupled to a first terminal, and a conductive barrier layer is adjacent to the second side of the dielectric layer and is coupled to a second terminal. The conductive barrier layer may be formed from tungsten nitride, tungsten silicon nitride, titanium silicon nitride or other barrier materials.