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272 条记录 (耗时 0.036 秒)

    Method of heating semiconductor wafer to improve wafer flatness
    31.
    发明申请
    Method of heating semiconductor wafer to improve wafer flatness 有权
    加热半导体晶片以提高晶圆平坦度的方法

    公开(公告)号：US20080014763A1

    公开(公告)日：2008-01-17

    申请号：US11486098

    申请日：2006-07-14

    申请人： Hsiao-Tzu Lu ,  Burn-Jeng Lin ,  Chin-Hsiang Lin ,  Kuei-Shun Chen ,  Tsai-Sheng Gau

    发明人： Hsiao-Tzu Lu ,  Burn-Jeng Lin ,  Chin-Hsiang Lin ,  Kuei-Shun Chen ,  Tsai-Sheng Gau

    IPC分类号： H01L21/00

    CPC分类号： H01L21/67115 ,  H01L21/26513 ,  H01L21/2686

    摘要： A method of heating-treating a semiconductor wafer is provided. In one embodiment, a first layer is formed over a first side of a substrate. A second layer is formed over the first layer and over a second side of the substrate and the wafer is then flash annealed. In another embodiment, a first layer is formed over a first side of a substrate and over a second side of the substrate. A second layer is formed over the first layers and the wafer is then flash annealed.

    摘要翻译： 提供了一种加热处理半导体晶片的方法。 在一个实施例中，在衬底的第一侧上形成第一层。 第二层形成在衬底的第一层和第二侧上，然后闪光退火晶片。 在另一个实施例中，第一层形成在衬底的第一侧上并且在衬底的第二侧上方。 在第一层上形成第二层，然后闪晶退火晶片。

    Semiconductor device with scattering bars adjacent conductive lines
    32.
    发明申请
    Semiconductor device with scattering bars adjacent conductive lines 有权
    具有相邻导线的散射棒的半导体器件

    公开(公告)号：US20050277067A1

    公开(公告)日：2005-12-15

    申请号：US10867076

    申请日：2004-06-14

    申请人： Kuei Shun Chen ,  Chin-Hsiang Lin ,  Yung-Sung Yen ,  Chih-Ming Lai

    发明人： Kuei Shun Chen ,  Chin-Hsiang Lin ,  Yung-Sung Yen ,  Chih-Ming Lai

    IPC分类号： G03F7/00 ,  H01L21/311 ,  H01L21/768

    CPC分类号： H01L21/31144 ,  H01L21/76838

    摘要： A semiconductor device and method of manufacture thereof wherein scattering bars are disposed on both sides of an isolated conductive line of a semiconductor device to improve the lithography results. The scattering bars have a sufficient width and are spaced a sufficient distance from the isolated conductive line so as to increase the depth of focus of the isolated conductive line during the patterning of the semiconductor device. The scattering bars are left remaining in the finished semiconductor device after the manufacturing process is completed.

    摘要翻译： 一种半导体器件及其制造方法，其中散射棒设置在半导体器件的隔离导电线的两侧，以改善光刻结果。 散射棒具有足够的宽度并且与隔离导电线隔开足够的距离，以便在半导体器件的图案化期间增加隔离导线的焦深。 在制造过程完成之后，散射棒留在完成的半导体器件中。

    Plasma etcher design with effective no-damage in-situ ash
    34.
    发明授权
    Plasma etcher design with effective no-damage in-situ ash 有权

    公开(公告)号：US09786471B2

    公开(公告)日：2017-10-10

    申请号：US13337418

    申请日：2011-12-27

    申请人： Ying Xiao ,  Chin-Hsiang Lin

    发明人： Ying Xiao ,  Chin-Hsiang Lin

    IPC分类号： H01J37/32 ,  G03F7/42 ,  H01L21/311

    CPC分类号： H01J37/321 ,  G03F7/427 ,  H01J37/32596 ,  H01J37/32706 ,  H01J37/32807 ,  H01J37/32889 ,  H01J37/32899 ,  H01L21/31138

    摘要： In some embodiments, the present disclosure relates to a plasma etching system having direct and localized plasma sources in communication with a processing chamber. The direct plasma is operated to provide a direct plasma to the processing chamber for etching a semiconductor workpiece. The direct plasma has a high potential, formed by applying a large bias voltage to the workpiece. After etching is completed the bias voltage and direct plasma source are turned off. The localized plasma source is then operated to provide a low potential, localized plasma to a position within the processing chamber that is spatially separated from the workpiece. The spatial separation results in formation of a diffused plasma having a zero/low potential that is in contact with the workpiece. The zero/low potential of the diffused plasma allows for reactive ashing to be performed, while mitigating workpiece damage resulting from ion bombardment caused by positive plasma potentials.

    Systems and methods of automatic boundary control for semiconductor processes
    36.
    发明授权
    Systems and methods of automatic boundary control for semiconductor processes 有权
    半导体工艺自动边界控制系统和方法

    公开(公告)号：US09250619B2

    公开(公告)日：2016-02-02

    申请号：US13311601

    申请日：2011-12-06

    申请人： Chih-Wei Hsu ,  Mei-Jen Wu ,  Yen-Di Tsen ,  Jo Fei Wang ,  Jong-I Mou ,  Chin-Hsiang Lin

    发明人： Chih-Wei Hsu ,  Mei-Jen Wu ,  Yen-Di Tsen ,  Jo Fei Wang ,  Jong-I Mou ,  Chin-Hsiang Lin

    IPC分类号： G06F19/00 ,  G05B19/18 ,  H01L21/66

    CPC分类号： G05B19/18 ,  G05B2219/45031 ,  H01L22/20

    摘要： A system and method of automatically calculating boundaries for a semiconductor fabrication process. The method includes selecting a first parameter for monitoring during a semiconductor fabrication process. A first set of values for the first parameter are received and a group value of the first set is determined. Each value in the first set of values is normalized. A first weighting factor is selected based on a number of values in the first set. The embodiment also includes generating a first and a second boundary value as a function of the weighting factor, the first set normalized values and the group value of the first set and applying the first and second boundary values to control the semiconductor fabrication process.

    摘要翻译： 一种自动计算半导体制造工艺边界的系统和方法。 该方法包括在半导体制造过程中选择用于监测的第一参数。 接收第一参数的第一组值，并确定第一组的组值。 第一组值中的每个值都被归一化。 基于第一组中的值的数量来选择第一加权因子。 该实施例还包括根据加权因子，第一集合归一化值和第一组的组值产生第一和第二边界值，并施加第一和第二边界值以控制半导体制造过程。

    Closed loop control for reliability
    38.
    发明授权
    Closed loop control for reliability 有权
    闭环控制可靠性

    公开(公告)号：US09026241B2

    公开(公告)日：2015-05-05

    申请号：US13404676

    申请日：2012-02-24

    申请人： Wen-Cheng Yang ,  Chung-En Kao ,  You-Hua Chou ,  Ming-Chih Tsai ,  Chen-Chia Chiang ,  Bo-Hung Lin ,  Chin-Hsiang Lin

    发明人： Wen-Cheng Yang ,  Chung-En Kao ,  You-Hua Chou ,  Ming-Chih Tsai ,  Chen-Chia Chiang ,  Bo-Hung Lin ,  Chin-Hsiang Lin

    IPC分类号： G06F19/00 ,  G05B9/03

    CPC分类号： G05B9/03 ,  G05B23/0237 ,  G05B2219/37533 ,  G05B2219/45031

    摘要： The present disclosure relates to semiconductor tool monitoring system having multiple sensors configured to concurrently and independently monitor processing conditions of a semiconductor manufacturing tool. In some embodiments, the disclosed tool monitoring system comprises a first sensor system configured to monitor one or more processing conditions of a semiconductor manufacturing tool and to generate a first monitoring response based thereupon. A redundant, second sensor system is configured to concurrently monitor the one or more processing conditions of the manufacturing tool and to generate a second monitoring response based thereupon. A comparison element is configured to compare the first and second monitoring responses, and if the responses deviate from one another (e.g., have a deviation greater than a threshold value) to generate a warning signal. By comparing the first and second monitoring responses, errors in the sensor systems can be detected in real time, thereby preventing yield loss.

    摘要翻译： 本公开涉及具有多个传感器的半导体工具监视系统，其被配置为同时且独立地监视半导体制造工具的处理条件。 在一些实施例中，所公开的工具监控系统包括被配置为监视半导体制造工具的一个或多个处理条件并基于此产生第一监视响应的第一传感器系统。 冗余的第二传感器系统被配置为同时监视制造工具的一个或多个处理条件并且基于此产生第二监视响应。 比较元件被配置为比较第一和第二监测响应，以及如果响应彼此偏离（例如，具有大于阈值的偏差）以产生警告信号。 通过比较第一和第二监测响应，可以实时检测传感器系统中的误差，从而防止产量损失。

    Method of fabricating an integrated circuit device
    39.
    发明授权
    Method of fabricating an integrated circuit device 有权
    制造集成电路器件的方法

    公开(公告)号：US08921177B2

    公开(公告)日：2014-12-30

    申请号：US13189108

    申请日：2011-07-22

    申请人： Ming-Hsi Yeh ,  Hsien-Hsin Lin ,  Ying-Hsueh Chang Chien ,  Yi-Fang Pai ,  Chi-Ming Yang ,  Chin-Hsiang Lin

    发明人： Ming-Hsi Yeh ,  Hsien-Hsin Lin ,  Ying-Hsueh Chang Chien ,  Yi-Fang Pai ,  Chi-Ming Yang ,  Chin-Hsiang Lin

    IPC分类号： H01L21/8238 ,  H01L21/20

    CPC分类号： H01L29/665 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  Y10S438/976

    摘要： A method for fabricating an integrated device is disclosed. A protective layer is formed over a gate structure when forming epitaxial (epi) features adjacent to another gate structure uncovered by the protective layer. The protective layer is thereafter removed after forming the epitaxial (epi) features. The disclosed method provides an improved method for removing the protective layer without substantial defects resulting. In an embodiment, the improved formation method is achieved by providing a protector over an oxide-base material, and then removing the protective layer using a chemical comprising hydrofluoric acid.

    摘要翻译： 公开了一种用于制造集成器件的方法。 当形成与由保护层未覆盖的另一个栅极结构相邻的外延（epi）特征时，在栅极结构上形成保护层。 此后，在形成外延（epi）特征之后，去除保护层。 所公开的方法提供了用于去除保护层而没有实质缺陷的改进方法。 在一个实施方案中，改进的形成方法通过在氧化物基材料上提供保护剂，然后使用包含氢氟酸的化学品除去保护层来实现。

    Enhanced scanner throughput system and method
    40.
    发明授权
    Enhanced scanner throughput system and method 有权
    增强扫描仪吞吐量系统和方法

    公开(公告)号：US08906599B2

    公开(公告)日：2014-12-09

    申请号：US13473695

    申请日：2012-05-17

    申请人： Yu-Mei Liu ,  Chin-Hsiang Lin ,  Heng-Hsin Liu ,  Heng-Jen Lee ,  I-Hsiung Huang ,  Chih-Wei Lin

    发明人： Yu-Mei Liu ,  Chin-Hsiang Lin ,  Heng-Hsin Liu ,  Heng-Jen Lee ,  I-Hsiung Huang ,  Chih-Wei Lin

    IPC分类号： G03F7/20

    CPC分类号： G03F7/70358

    摘要： A method and system to improve scanner throughput is provided. An image from a reticle is projected onto a substrate using a continuous linear scanning procedure in which an entire column of die or cells of die is scanned continuously, i.e. without stepping to a different location. Each scan includes translating a substrate with respect to a fixed beam. While the substrate is translated, the reticle is also translated. When a first die or cell of die is projected onto the substrate, the reticle translates along a direction opposite the scan direction and as the scan continues along the same direction, the reticle then translates in the opposite direction of the substrate thereby forming an inverted pattern on the next die or cell. The time associated with exposing the substrate is minimized as the stepping operation only occurs after a complete column of cells is scanned.

    摘要翻译： 提供了一种提高扫描仪吞吐量的方法和系统。 使用连续线性扫描程序将来自掩模版的图像投影到基板上，其中连续扫描整列管芯或裸片的单元，即不进入不同的位置。 每个扫描包括相对于固定光束平移衬底。 当底物被翻译时，掩模版也被翻译。 当模具的第一裸片或裸片投影到衬底上时，标线沿着与扫描方向相反的方向平移，并且随着扫描沿着相同的方向继续，标线片然后沿着衬底的相反方向平移，从而形成倒置图案 在下一个死亡或细胞。 与曝光底物相关的时间最小化，因为步进操作仅在扫描完整的单元格列之后才发生。