公开(公告)号：US10236215B1

公开(公告)日：2019-03-19

申请号：US15791711

申请日：2017-10-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Youngtag Woo ,  Daniel Chanemougame ,  Bipul C. Paul ,  Lars W. Liebmann ,  Heimanu Niebojewski ,  Xuelian Zhu ,  Lei Sun ,  Hui Zang

IPC: H01L21/8234 ,  H01L21/768 ,  H01L23/522 ,  H01L27/088 ,  H01L23/528

Abstract: One illustrative method disclosed includes, among other things, forming an initial gate-to-source/drain (GSD) contact structure and an initial CB gate contact structure, wherein an upper surface of each of these contact structures are positioned at a first level. In one example, this method also includes forming a masking layer that covers the initial CB gate contact structure and exposes the initial GSD contact structure and, with the masking layer in position, performing a recess etching process on the initial GSD contact structure so as to form a recessed GSD contact structure, wherein a recessed upper surface of the recessed GSD contact structure is positioned at a second level that is below the first level.

公开(公告)号：US10217864B2

公开(公告)日：2019-02-26

申请号：US15592444

申请日：2017-05-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Josef Watts

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/49

Abstract: A semiconductor structure includes a substrate and a vertical FinFET disposed over the substrate. The vertical FinFET includes: a bottom source/drain (S/D) region disposed over the substrate, a fin extending vertically upwards from the bottom S/D region, the fin having a first (1st) sidewall, a second (2nd) sidewall and a top portion, an upper S/D region disposed over the top portion of the fin, the fin defining a channel between the bottom S/D region and the upper S/D region, a 1st gate structure having a 1st metal gate, the 1st gate structure disposed on the 1st sidewall of the fin, and a 2nd gate structure having a 2nd metal gate, the 2nd gate structure disposed on the 2nd sidewall of the fin. The 1st and 2nd metal gates are electrically isolated from each other by the fin.

公开(公告)号：US10177157B2

公开(公告)日：2019-01-08

申请号：US15792527

申请日：2017-10-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Min-hwa Chi

IPC: H01L27/11 ,  H01L21/82 ,  H01L27/092 ,  H01L21/8238

Abstract: A semiconductor structure includes a semiconductor substrate, at least one first elongated region of n-type or p-type, and at least one other second elongated region of the other of n-type or p-type, the first and second elongated regions crossing such that the first elongated region and the second elongated region intersect at a common area, and a shared gate structure over each common area.

公开(公告)号：US10170473B1

公开(公告)日：2019-01-01

申请号：US15811745

申请日：2017-11-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Josef S. Watts ,  Yi Qi

IPC: H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/02 ,  H01L21/266 ,  H01L29/66 ,  H01L29/06

Abstract: A method of forming an integrated circuit includes forming a FinFET by: forming a semiconductor fin on a semiconductor substrate; forming a first source/drain region in the semiconductor substrate under a first end of the semiconductor fin and a second source/drain region in the semiconductor substrate under a second, opposing end of the semiconductor fin, the second source/drain region separated from the first source/drain region by a portion of the semiconductor substrate having an opposite doping from that of the first and second source/drain region; and forming a surrounding gate extending about the semiconductor fin above the semiconductor substrate. A second vertical FinFET may be formed simultaneously. The method allows the FinFET to have a long channel extending laterally through its fin compared to the short channel of the vertical FinFET, thus creating short channel and long channel devices together without impacting vertical FinFET height.

公开(公告)号：US10163915B1

公开(公告)日：2018-12-25

申请号：US15634227

申请日：2017-06-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Jerome Ciavatti

IPC: H01L27/11 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/306 ,  H01L21/311 ,  H01L21/768

Abstract: A vertical SRAM cell includes a first (1st) inverter having a 1st pull-up (PU) transistor and a 1st pull-down (PD) transistor. The 1st PU and 1st PD transistors have a bottom source/drain (S/D) region disposed on a substrate and a channel extending upwards from a top surface of the bottom S/D region. A second (2nd) inverter has a 2nd PU transistor and a 2nd PD transistor. The 2nd PU and 2nd PD transistors have a bottom S/D region disposed on the substrate and a channel extending upwards from a top surface of the bottom S/D region. A 1st metal contact is disposed on sidewalls, and not on the top surface, of the bottom S/D regions of the 1st PU and 1st PD transistors. A 2nd metal contact is disposed on sidewalls, and not on the top surface, of the bottom S/D regions of the 2nd PU and 2nd PD transistors.

公开(公告)号：US10157927B2

公开(公告)日：2018-12-18

申请号：US15404754

申请日：2017-01-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Manfred Eller

IPC: H01L27/088 ,  H01L27/108 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/78

Abstract: A semiconductor memory device includes, for example, a substrate having a fin having a web portion extending from the substrate and a first overhanging fin portion extending outward from the web portion and spaced from the substrate, the fin comprising a source/drain region in the web portion of the fin, a first source/drain region in the first overhanging fin portion, an isolation material surrounding the web portion and disposed under the first overhanging fin portion of the fin, an upper surface of the isolation material being below an upper surface of the fin, a first gate disposed over the fin between the source/drain region in the web portion of the fin and the first source/drain region in the first overhanging fin portion of the fin, and a capacitor operably electrically connected to the first source/drain region in the first overhanging fin portion.

公开(公告)号：US10153209B1

公开(公告)日：2018-12-11

申请号：US15888408

申请日：2018-02-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guowei Xu ,  Hui Zang ,  Haiting Wang ,  Yue Zhong

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/3213 ,  H01L21/311 ,  H01L27/088 ,  H01L27/02 ,  H01L21/027 ,  H01L21/02 ,  H01L21/3105

Abstract: One illustrative integrated circuit product disclosed herein includes a first final gate structure, a second final gate structure and an insulating gate separation structure positioned between the first and second final gate structures. In this example, the insulating gate separation structure comprises an upper portion and a lower portion. The lower portion has a first lateral width in a first direction that is substantially uniform throughout a vertical height of the lower portion. The upper portion has a substantially uniform second lateral width in the first direction that is substantially uniform throughout a vertical height of the upper portion, wherein the second lateral width is less than the first lateral width.

公开(公告)号：US10147802B2

公开(公告)日：2018-12-04

申请号：US15160591

申请日：2016-05-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Manfred Eller ,  Min-hwa Chi

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L27/11 ,  H01L27/12 ,  H01L27/02

Abstract: Circuit structures, such as inverters and static random access memories, and fabrication methods thereof are presented. The circuit structures include, for instance: a first transistor, the first transistor having a first channel region disposed above an isolation region; and a second transistor, the second transistor having a second channel region, the second channel region being laterally adjacent to the first channel region of the first transistor and vertically spaced apart therefrom by the isolation region thereof. In one embodiment, the first channel region and the isolation region of the first transistor are disposed above a substrate, and the substrate includes the second channel region of the second transistor. In another embodiment, the first transistor includes a fin structure extending from the substrate, and an upper portion of the fin structure includes the first channel region and a lower portion of the fin structure includes the isolation region.

公开(公告)号：US10134739B1

公开(公告)日：2018-11-20

申请号：US15661058

申请日：2017-07-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Jerome Ciavatti ,  Rinus Tek Po Lee

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/108 ,  H01L27/115 ,  H01L29/06 ,  H01L29/10 ,  H01L21/8242 ,  H01L21/336 ,  H01L21/28

Abstract: Disclosed is a structure wherein lower source/drain regions of vertical field effect transistors (VFETs) of memory cells in a memory array are aligned above and electrically connected to buried bitlines. Each cell includes a VFET with a lower source/drain region, an upper source/drain region and at least one channel region extending vertically between the source/drain regions. The lower source/drain region is above and immediately adjacent to a buried bitline, which has the same or a narrower width than the lower source/drain region and which includes a pair of bitline sections and a semiconductor region positioned laterally between the sections. The semiconductor region is made of a different semiconductor material than the lower source/drain region. Also disclosed is a method that ensures that bitlines of a desired critical dimension can be achieved and that allows for size scaling of the memory array with minimal bitline coupling.

公开(公告)号：US20180331097A1

公开(公告)日：2018-11-15

申请号：US15592172

申请日：2017-05-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Rinus Tek Po Lee

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/764

CPC classification number: H01L27/0886 ,  H01L21/764 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823481

Abstract: A method, apparatus and system are disclosed herein for a finFET device having an air gap spacer and/or a tapered bottom dielectric spacer for reducing parasitic capacitance. A first source/drain (S/D) region is formed on a substrate. A set of fin structures are formed above the first S/D region. A gate region is formed above the first S/D region and adjacent at least a portion of the fin structures. A space for an air gap is formed above the gate region. A top epitaxial (EPI) feature is formed extending over the space for the air gap, thereby forming an air gap spacer between the top epitaxial feature and the gate region.