公开(公告)号：US09318436B2

公开(公告)日：2016-04-19

申请号：US14470213

申请日：2014-08-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Larry Zhao ,  Ming He ,  Sean Lin ,  John Iacoponi ,  Errol Todd Ryan

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76873 ,  H01L23/5226 ,  H01L23/53233 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a barrier layer in the trench/via, forming a copper-based seed layer on the barrier layer, converting at least a portion of the copper-based seed layer into a copper-based nitride layer, depositing a bulk copper-based material on the copper-based nitride layer so as to overfill the trench/via and performing at least one chemical mechanical polishing process to remove excess materials positioned outside of the trench/via to thereby define a copper-based conductive structure. A device disclosed herein includes a layer of insulating material, a copper-based conductive structure positioned in a trench/via within the layer of insulating material and a copper-based silicon or germanium nitride layer positioned between the copper-based conductive structure and the layer of insulating material.

Abstract translation: 本文公开的一种说明性方法包括在绝缘材料层中形成沟槽/通孔，在沟槽/通孔中形成阻挡层，在阻挡层上形成铜基种子层，将至少一部分铜基 种子层形成铜基氮化物层，在铜基氮化物层上沉积大块铜基材料，以覆盖沟槽/通孔，并执行至少一种化学机械抛光工艺，以去除位于沟槽之外的多余材料 / via，从而限定铜基导电结构。 本文公开的装置包括绝缘材料层，位于绝缘材料层内的沟槽/通孔中的铜基导电结构以及位于铜基导电结构和层之间的铜基硅或氮化锗层 的绝缘材料。

公开(公告)号：US20150255340A1

公开(公告)日：2015-09-10

申请号：US14202268

申请日：2014-03-10

Applicant: GLOBALFOUNDRIES, Inc. ,  Intermolecular Inc.

Inventor： Anh Duong ,  Errol Todd Ryan

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76843 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76883 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Copper can be etched with selectivity to Ta/TaN barrier liner and SiC hardmask layers, for example, to reduce the potential copper contamination. The copper film can be recessed more than the liner to further enhance the protection. Wet etch solutions including a mixture of HF and HCl can be used for selective etching copper with respect to the liner material, for example, the copper film can be recessed between 2 and 3 nm, and the barrier liner film can be recessed between 1.5 and 2 nm.

Abstract translation: 可以选择性地对Ta / TaN阻挡衬垫和SiC硬掩模层进行蚀刻，例如，以减少潜在的铜污染。 铜膜可以比衬垫更凹入，以进一步增强保护。 可以使用包含HF和HCl的混合物的湿式蚀刻溶液来相对于衬垫材料选择性地蚀刻铜，例如，铜膜可以凹陷在2和3nm之间，并且阻挡衬里膜可以凹陷在1.5和 2 nm。

公开(公告)号：US20150130065A1

公开(公告)日：2015-05-14

申请号：US14075228

申请日：2013-11-08

Applicant: GLOBALFOUNDRIES, Inc. ,  Intermolecular Inc.

Inventor： Anh Duong ,  Errol Todd Ryan

IPC: H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5329 ,  C23F1/02 ,  C23F1/18 ,  C23F1/26 ,  H01L21/32134 ,  H01L21/76834 ,  H01L21/76883 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Copper can be etched with selectivity to Ta/TaN barrier liner and SiC hardmask layers, for example, to reduce the potential copper contamination. The copper film can be recessed more than the liner to further enhance the protection. Wet etch solutions including a mixture of HF and H2SO4 can be used for selective etching copper with respect to the liner material, for example, the copper film can be recessed between 2 and 3 nm, and the barrier liner film can be recessed between 1.5 and 2 nm.

Abstract translation: 可以选择性地对Ta / TaN阻挡衬垫和SiC硬掩模层进行蚀刻，例如，以减少潜在的铜污染。 铜膜可以比衬垫更凹入，以进一步增强保护。 包括HF和H 2 SO 4的混合物的湿蚀刻溶液可用于相对于衬垫材料选择性蚀刻铜，例如，铜膜可以凹陷在2和3nm之间，并且阻挡衬里膜可以凹入1.5和 2 nm。

公开(公告)号：US08980740B2

公开(公告)日：2015-03-17

申请号：US13786627

申请日：2013-03-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Errol Todd Ryan ,  Xunyuan Zhang

IPC: H01L21/4763 ,  H01L21/768

CPC classification number: H01L21/76843 ,  H01L21/76814 ,  H01L21/76826 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A process of modulating the thickness of a barrier layer deposited on the sidewalls and floor of a recessed feature in a semiconductor substrate is disclosed. The process includes altering the surface of the conductive feature on which the barrier layer is deposited by annealing in a reducing atmosphere and optionally additionally, silylating the dielectric surface that forms the sidewalls of the recessed feature.

Abstract translation: 公开了一种调制沉积在半导体衬底中凹陷特征的侧壁和底板上的阻挡层的厚度的工艺。 该方法包括通过在还原气氛中进行退火来改变其上沉积阻挡层的导电特征的表面，以及任选地另外地使形成凹陷特征的侧壁的电介质表面甲硅烷基化。

公开(公告)号：US20140361435A1

公开(公告)日：2014-12-11

申请号：US14470213

申请日：2014-08-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Larry Zhao ,  Ming He ,  Sean Lin ,  John Iacoponi ,  Errol Todd Ryan

IPC: H01L23/532 ,  H01L23/522

CPC classification number: H01L23/53238 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76873 ,  H01L23/5226 ,  H01L23/53233 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a barrier layer in the trench/via, forming a copper-based seed layer on the barrier layer, converting at least a portion of the copper-based seed layer into a copper-based nitride layer, depositing a bulk copper-based material on the copper-based nitride layer so as to overfill the trench/via and performing at least one chemical mechanical polishing process to remove excess materials positioned outside of the trench/via to thereby define a copper-based conductive structure. A device disclosed herein includes a layer of insulating material, a copper-based conductive structure positioned in a trench/via within the layer of insulating material and a copper-based silicon or germanium nitride layer positioned between the copper-based conductive structure and the layer of insulating material.

Abstract translation: 本文公开的一种说明性方法包括在绝缘材料层中形成沟槽/通孔，在沟槽/通孔中形成阻挡层，在阻挡层上形成铜基种子层，将至少一部分铜基 种子层形成铜基氮化物层，在铜基氮化物层上沉积大块铜基材料，以覆盖沟槽/通孔，并执行至少一种化学机械抛光工艺，以去除位于沟槽之外的多余材料 / via，从而限定铜基导电结构。 本文公开的装置包括绝缘材料层，位于绝缘材料层内的沟槽/通孔中的铜基导电结构以及位于铜基导电结构和层之间的铜基硅或氮化锗层 的绝缘材料。

公开(公告)号：US10283372B2

公开(公告)日：2019-05-07

申请号：US15705956

申请日：2017-09-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sean Xuan Lin ,  Xunyuan Zhang ,  Mark V. Raymond ,  Errol Todd Ryan ,  Nicholas V. LiCausi

IPC: H01L27/10 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/532

Abstract: Methods of forming interconnects. An interconnect opening is formed in a dielectric layer. A first conductor layer composed of a first metal is formed in the interconnect opening. A second conductor layer is formed inside the interconnect opening by displacing the first metal of the first conductor layer and replacing the first metal with a second metal different from the first metal.

公开(公告)号：US10199261B1

公开(公告)日：2019-02-05

申请号：US15653638

申请日：2017-07-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： James McMahon ,  Ryan S. Smith ,  Nicholas V. LiCausi ,  Errol Todd Ryan ,  Xunyuan Zhang ,  Shao Beng Law

IPC: H01L21/768 ,  H01L23/522

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to dielectric repair for via and skip via structures and methods of manufacture. The method includes: etching a via structure in a dielectric layer; repairing sidewalls of the via structure with a repair agent; and extending the via structure with an additional etching into a lower dielectric layer to form a skip via structure exposing a metallization layer.

公开(公告)号：US20190021176A1

公开(公告)日：2019-01-17

申请号：US15647400

申请日：2017-07-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shao Beng Law ,  Nicholas V. LiCausi ,  Errol Todd Ryan ,  James McMahon ,  Ryan S. Smith ,  Xunyuan Zhang

IPC: H05K3/46 ,  H05K3/40 ,  H05K1/11

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to via and skip via structures and methods of manufacture. The method includes: forming a first metallization layer with a first capping layer over the first metallization layer; forming a second metallization layer with a second capping layer over the second metallization layer; forming a partial skip via structure to the first metallization layer by removing a portion of the first capping layer and the second capping and depositing conductive material in an opening formed in the second metallization layer; forming a third capping layer over the filled partial skip via and the second capping layer; and forming a remaining portion of a skip via structure in alignment with the partial skip via structure by opening the third capping layer to expose the conductive material of the partial skip via.

公开(公告)号：US10177028B1

公开(公告)日：2019-01-08

申请号：US15643742

申请日：2017-07-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Nicholas V. LiCausi ,  Errol Todd Ryan

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to fully aligned via structures having relaxed gapfills and methods of manufacture. The method includes: selectively depositing a capping material on a conductive material within a plurality of interconnect structures to form capped interconnect structures; depositing at least one insulator material over the capped interconnect structures; forming a fully aligned via structure through the at least one insulator material to expose the capping material; filling the fully aligned via structure with an alternative metal; and depositing a metal material on the alternative metal in the fully aligned via structure.

公开(公告)号：US10170330B2

公开(公告)日：2019-01-01

申请号：US14812046

申请日：2015-07-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Errol Todd Ryan

IPC: H01L21/3105 ,  H01L21/311 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768

Abstract: Semiconductor structure and methods of fabrication thereof are provided which includes, for instance, providing a carbon-doped material layer within a recess of a semiconductor structure; removing, in part, carbon from the carbon-doped material layer to obtain, at least in part, a carbon-depleted region thereof, the carbon-depleted region having a modified etch property with an increased etch rate compared to an etch rate of the carbon-doped material layer; and recessing the carbon-depleted region of the carbon-doped material layer by an etching process, with the carbon-depleted region being recessed based upon, in part, the modified etch property of the carbon-depleted region.