公开(公告)号：US11271077B2

公开(公告)日：2022-03-08

申请号：US16807453

申请日：2020-03-03

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. Stamper ,  Vibhor Jain ,  John J. Pekarik ,  Steven M. Shank ,  John J. Ellis-Monaghan

IPC: H01L27/01 ,  H01L21/76 ,  H01L29/06 ,  H01L29/04 ,  H01L21/762 ,  H01L27/102 ,  H01L29/737 ,  H01L27/12 ,  H01L21/324 ,  H01L29/32

Abstract: Structures including electrical isolation and methods of forming a structure including electrical isolation. A semiconductor layer is formed over a semiconductor substrate and shallow trench isolation regions are formed in the semiconductor layer. The semiconductor layer includes single-crystal semiconductor material having an electrical resistivity that is greater than or equal to 1000 ohm-cm. The shallow trench isolation regions are arranged to surround a portion of the semiconductor layer to define an active device region. A polycrystalline layer is positioned in the semiconductor layer and extends laterally beneath the active device region and the shallow trench isolation regions that surround the active device region.

公开(公告)号：US11205701B1

公开(公告)日：2021-12-21

申请号：US16899086

申请日：2020-06-11

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Henry Aldridge ,  John J. Ellis-Monaghan ,  Michel J. Abou-Khalil

IPC: H01L29/10 ,  H01L29/08 ,  H01L27/092 ,  H01L21/8238

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure is formed over a channel region of a substrate. A first source/drain region is positioned in the substrate adjacent to a first sidewall of the gate structure, a second source/drain region is positioned in the substrate adjacent to a second sidewall of the gate structure, and an extension region is positioned in the substrate. The extension region includes first and second sections that each overlap with the first source/drain region. The first and second sections of the extension region are spaced apart along a longitudinal axis of the gate structure. A portion of the channel region is positioned along the longitudinal axis of the gate structure between the first and second sections of the extension region.

公开(公告)号：US20210376159A1

公开(公告)日：2021-12-02

申请号：US16890063

申请日：2020-06-02

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Michel J. Abou-Khalil ,  Steven M. Shank ,  Mark Levy ,  Rajendran Krishnasamy ,  John J. Ellis-Monaghan ,  Anthony K. Stamper

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/06 ,  H01L21/763

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A shallow trench isolation region is formed in a semiconductor substrate. A trench is formed in the shallow trench isolation region, and a body region is formed in the trench of the shallow trench isolation region. The body region is comprised of a polycrystalline semiconductor material.

公开(公告)号：US11063140B2

公开(公告)日：2021-07-13

申请号：US16784683

申请日：2020-02-07

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： John J. Pekarik ,  Anthony K. Stamper ,  Vibhor Jain ,  Steven M. Shank ,  John J. Ellis-Monaghan ,  Herbert Ho ,  Qizhi Liu

IPC: H01L29/737 ,  H01L29/66 ,  H01L29/08 ,  H01L29/423 ,  H01L27/082

Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. A first heterojunction bipolar transistor includes a first emitter, a first collector, and a first base layer having a portion positioned between the first emitter and the first collector. A second heterojunction bipolar transistor includes a second emitter, a second collector, and a second base layer having a portion positioned between the second emitter and the second collector. The first and second base layers each comprise silicon-germanium, the first base layer includes a first germanium profile, and the second base layer includes a second germanium profile that is identical to the first germanium profile.

公开(公告)号：US20210098612A1

公开(公告)日：2021-04-01

申请号：US16784683

申请日：2020-02-07

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： John J. Pekarik ,  Anthony K. Stamper ,  Vibhor Jain ,  Steven M. Shank ,  John J. Ellis-Monaghan ,  Herbert Ho ,  Qizhi Liu

IPC: H01L29/737 ,  H01L29/423 ,  H01L29/08 ,  H01L29/66

Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. A first heterojunction bipolar transistor includes a first emitter, a first collector, and a first base layer having a portion positioned between the first emitter and the first collector. A second heterojunction bipolar transistor includes a second emitter, a second collector, and a second base layer having a portion positioned between the second emitter and the second collector. The first and second base layers each comprise silicon-germanium, the first base layer includes a first germanium profile, and the second base layer includes a second germanium profile that is identical to the first germanium profile.

公开(公告)号：US12170313B2

公开(公告)日：2024-12-17

申请号：US18324637

申请日：2023-05-26

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor Jain ,  Anthony K. Stamper ,  John J. Ellis-Monaghan ,  Steven M. Shank ,  Rajendran Krishnasamy

IPC: H01L29/06 ,  H01L21/763 ,  H01L29/08 ,  H01L29/165 ,  H01L29/66 ,  H01L29/737

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich region and methods of manufacture. The structure includes: a trap rich isolation region embedded within the bulk substrate; and a heterojunction bipolar transistor above the trap rich isolation region, with its sub-collector region separated by the trap rich isolation region by a layer of the bulk substrate.

公开(公告)号：US20240186429A1

公开(公告)日：2024-06-06

申请号：US18062201

申请日：2022-12-06

Applicant: GlobalFoundries U.S. Inc.

Inventor： Rajendran Krishnasamy ,  John J. Ellis-Monaghan ,  Siva P. Adusumilli ,  Ramsey M. Hazbun

IPC: H01L31/0224 ,  H01L31/0312 ,  H01L31/103 ,  H01L31/18

CPC classification number: H01L31/022408 ,  H01L31/03125 ,  H01L31/1037 ,  H01L31/1812

Abstract: A photodiode and a related method of manufacture are disclosed. The photodiode includes a transfer gate and a floating diffusion adjacent to the transfer gate. In addition, the photodiode includes an upper terminal; an intrinsic semiconductor region in contact with the upper terminal, the intrinsic semiconductor region in a trench in a substrate adjacent to the transfer gate; and a lower terminal in contact with the intrinsic semiconductor region. An insulator layer is along an entirety of a sidewall of the intrinsic semiconductor region and between the intrinsic semiconductor region and the transfer gate. A p-type well may also optionally be between the insulator layer and the transfer gate.

公开(公告)号：US20230387333A1

公开(公告)日：2023-11-30

申请号：US17664741

申请日：2022-05-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Siva P. Adusumilli ,  John J. Ellis-Monaghan ,  Rajendran Krishnasamy ,  Ramsey Hazbun

IPC: H01L31/0216 ,  H01L31/18 ,  H01L31/105

CPC classification number: H01L31/0216 ,  H01L31/1804 ,  H01L31/105 ,  H01L31/022408

Abstract: A photodetector structure includes a first semiconductor material layer on a first portion of a doped well in a substrate. The photodetector structure includes a second semiconductor layer over the first semiconductor layer. The first and second semiconductor material layers may include an undoped semiconductor material. The photodetector structure includes an insulative collar laterally surrounding the first and second semiconductor material layers. The insulative collar may include a varying horizontal thickness. The photodetector structure includes a doped semiconductor material having an opposite doping polarity relative to the doped well, and positioned over the second semiconductor material layer and the insulating collar.

公开(公告)号：US20230317869A1

公开(公告)日：2023-10-05

申请号：US17709181

申请日：2022-03-30

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Rajendran Krishnasamy ,  John J. Ellis-Monaghan ,  Siva P. Adusumilli ,  Ramsey Hazbun ,  Steven M. Shank

IPC: H01L31/105 ,  H01L31/0224 ,  H01L31/18

CPC classification number: H01L31/105 ,  H01L31/022408 ,  H01L31/1812

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photodiodes and methods of manufacture. The structure includes: a top terminal; an intrinsic material in contact with the top terminal; and a bottom terminal in contact with the intrinsic material, the bottom terminal including a P semiconductor material and a fully depleted N semiconductor material.

公开(公告)号：US11777043B1

公开(公告)日：2023-10-03

申请号：US17807887

申请日：2022-06-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ramsey M. Hazbun ,  John J. Ellis-Monaghan ,  Rajendran Krishnasamy ,  Siva P. Adusumilli

IPC: H01L31/0352

CPC classification number: H01L31/035281

Abstract: A substrate is formed to include a substrate base and a substrate extension. A photodiode contacts the substrate base. The substrate extension is adjacent the photodiode. An additional device contacts the substrate extension. A sidewall spacer contacts the photodiode and the substrate extension. The additional device includes conductive elements within the substrate extension adjacent the sidewall spacer.