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    Systems and methods for detecting flaws on a storage disk
    31.
    发明授权
    Systems and methods for detecting flaws on a storage disk 失效
    用于检测存储磁盘上的缺陷的系统和方法

    公开(公告)号：US07646556B1

    公开(公告)日：2010-01-12

    申请号：US11484893

    申请日：2006-07-10

    Applicant: K. Rickmer E. Kose ,  Bin Liu

    Inventor： K. Rickmer E. Kose ,  Bin Liu

    IPC: G11B5/40

    CPC classification number: G11B5/012 ,  G11B5/40 ,  G11B20/1816 ,  G11B27/36 ,  G11B2220/2516

    Abstract: A flaw scan system for detecting a location of first and second types of location specific anomalies on a storage disk of a hard disk drive comprising a write system, a read system, and first and second anomaly location systems. The write system writes a first set of bits to the storage disk in first and second data patterns. The read system reads the first set of bits from the storage disk. The first anomaly location system determines locations of the first type of location specific anomaly based on the first data pattern. The second anomaly location system determines locations of the second type of location specific anomaly based on the second data pattern.

    Abstract translation: 一种用于检测包括写入系统，读取系统以及第一和第二异常定位系统的硬盘驱动器的存储盘上的第一类型和第二类型的位置特定异常的位置的缺陷扫描系统。 写系统以第一和第二数据模式将第一组位写入存储盘。 读取系统从存储磁盘读取第一组位。 第一异常位置系统基于第一数据模式确定第一类型的位置特定异常的位置。 第二异常位置系统基于第二数据模式确定第二类型的位置特定异常的位置。

    Method and apparatus for sharing memory in a multiprocessor system
    34.
    发明申请
    Method and apparatus for sharing memory in a multiprocessor system 有权
    用于在多处理器系统中共享存储器的方法和装置

    公开(公告)号：US20070067511A1

    公开(公告)日：2007-03-22

    申请号：US11233597

    申请日：2005-09-22

    Applicant: Charbel Khawand ,  Jean Khawand ,  Bin Liu

    Inventor： Charbel Khawand ,  Jean Khawand ,  Bin Liu

    IPC: G06F5/00

    CPC classification number: G06F9/5016

    Abstract: A multiprocessor system (100) for sharing memory has a memory (102), and two or more processors (104). The processors are programmed to establish (202) memory buffer pools between the processors, and for each memory buffer pool, establish (204) an array of buffer pointers that point to corresponding memory buffers. The processors are further programmed to, for each array of buffer pointers, establish (206) a consumption pointer for the processor owning the memory buffer pool, and a release pointer for another processor sharing said memory buffer pool, each pointer initially pointing to a predetermined location of the array, and adjust (208-236) the consumption and release pointers according to buffers consumed and released.

    Abstract translation: 用于共享存储器的多处理器系统（100）具有存储器（102）和两个或更多个处理器（104）。 处理器被编程为在处理器之间建立（202）存储器缓冲池，并且对于每个存储器缓冲池，建立（204）指向相应的存储器缓冲器的缓冲器指针阵列（204）。 处理器进一步被编程为对于每个缓冲器指针阵列，建立（206）用于处理器拥有存储器缓冲池的消耗指针，以及用于共享所述存储器缓冲池的另一个处理器的释放指针，每个指针最初指向预定的 阵列的位置，并根据消耗和释放的缓冲区调整（208 - 236）消耗和释放指针。

    Cationic water-soluble conjugated polymers and their precursors
    38.
    发明申请
    Cationic water-soluble conjugated polymers and their precursors 审中-公开
    阳离子水溶性共轭聚合物及其前体

    公开(公告)号：US20060142522A1

    公开(公告)日：2006-06-29

    申请号：US10532649

    申请日：2003-10-23

    Applicant: Bin Liu

    Inventor： Bin Liu

    IPC: C08G77/00 ,  C08G73/00

    CPC classification number: C08G61/10 ,  C08G61/02 ,  H01B1/122

    Abstract: Conjugated polymers of the formula(I) wherein: • R1, and R2 are identical or different and are each H, a straight or branched alkyl, alkoxyl, ester groups or cyclic crown ether groups having from 1 to about 22 carbon atoms; • A, B, E and F are identical or different and are each H, Si R′R″ or NR′R″ (but can not all be H or SiR′R″); R′, and R″ are independently selected from the group consisting of hydrogen, unbranched or branched alkyl or alkoxyl groups having 1 to about 12 carbon atoms, (C3 to C10) cycloalkyl groups; • C and D are identical or different and are each H (but can not both be H), O, S, CO, COO, CRR′, NR′, Si R′R″, wherein R′ and R″ are as defined above; • R3, R4, R5, R6, R7 and R8 are identical or different and are independently selected from linear or branched or cyclical saturated or unsaturated aliphatic moieties which may contain one or more heteroatoms and which may contain one or more aromatic groups, substituted or unsubstituted aromatic moieties; - G is hydrogen, halogen, boronic acid, boronate radical or an aryl moiety; • a and b are independent and each is a number from 0 to about 100; • x and y are also independent and each is a number from 0 to about 100; and • n is a number from 1 to about 1000.

    Abstract translation: 式（I）的共轭聚合物，其中： R 1，R 2和R 2相同或不同，各自为H，具有1至约22个的直链或支链烷基，烷氧基，酯基或环冠醚基团 碳原子 。 A，B，E和F相同或不同，分别为H，SiR'R“或NR'R”（但不能全部为H或SiR'R“）; R'和R“独立地选自氢，具有1至约12个碳原子的无支链或支链烷基或烷氧基，（C3至C10）环烷基; 。 C和D相同或不同，各自为H（但不能均为H），O，S，CO，COO，CRR'，NR'，SiR'R“，其中R'和R”为 以上定义 。 R 3，R 4，R 5，R 6，R 7和R 7， R 8相同或不同，并且独立地选自可以含有一个或多个杂原子并且可以含有一个或多个芳族基团，取代或未取代的芳族部分的直链或支链或环状饱和或不饱和脂族部分 ; -G是氢，卤素，硼酸，硼酸根或芳基; 。 a和b是独立的，每个是从0到约100的数字; 。 x和y也是独立的，并且每个是从0到约100的数字; 和。 n是从1到约1000的数字。

    Enhanced interleave type error correction method and apparatus
    39.
    发明授权
    Enhanced interleave type error correction method and apparatus 有权
    增强型交错式纠错方法及装置

    公开(公告)号：US06981197B2

    公开(公告)日：2005-12-27

    申请号：US10057831

    申请日：2002-01-23

    Applicant: Bin Liu ,  Edmun ChianSong Seng ,  UttHeng Kan

    Inventor： Bin Liu ,  Edmun ChianSong Seng ,  UttHeng Kan

    IPC: G11B20/10 ,  G11B20/18 ,  H03M13/27 ,  G11C29/00

    CPC classification number: H03M13/27 ,  G11B20/10009 ,  G11B20/1866

    Abstract: An enhanced interleave type error correction method is provided in which decoding of an enhanced interleave block is done. Subsequently the decoding may be done by decoding the estimated codewords multiple times using a single error correction code. In addition, a decoder and a digital communication system for implementing the enhanced interleave type error correction method are provided.

    Abstract translation: 提供了一种增强的交错型纠错方法，其中完成了增强交错块的解码。 随后，可以使用单个纠错码通过多次对所估计的码字进行解码来完成解码。 此外，提供了一种用于实现增强型交错型纠错方法的解码器和数字通信系统。

    High noise rejection voltage-controlled ring oscillator architecture
    40.
    发明申请
    High noise rejection voltage-controlled ring oscillator architecture 失效

    公开(公告)号：US20050068114A1

    公开(公告)日：2005-03-31

    申请号：US10992426

    申请日：2004-11-18

    Applicant: Bin Liu

    Inventor： Bin Liu

    IPC: H03F3/45 ,  H03F3/72 ,  H03K3/0231 ,  H03K5/00 ,  H03K5/13 ,  H03L7/099 ,  H03B1/00

    CPC classification number: H03F3/45183 ,  H03F3/4565 ,  H03F3/72 ,  H03F2203/7203 ,  H03K3/0231 ,  H03K3/0322 ,  H03K5/133 ,  H03K2005/00208 ,  H03L7/0995

    Abstract: A ring oscillator circuit, such as a VCO, with a relatively high level of noise rejection for noise originating from both the voltage supply and ground. The ring oscillator circuit is composed of a plurality of differential delay circuits, each differential delay circuit generating a differential output signal that is a delayed (and preferably inverted) version of a differential input signal. ‘Each differential delay circuit includes first and second input transistors for receiving the differential input signal. Each differential delay circuit also includes first and second load transistors coupled in parallel with the respective first and second input transistors. Each differential delay circuit further includes a first current source coupled between the first input transistor and a first power supply terminal (e.g., a voltage supply terminal), a second current source coupled between the second input transistor and the first power supply terminal and a third current source coupled between the first and second input transistors and a second power supply terminal (e.g., a ground terminal). The first and second current sources reduce the coupling of noise from the first power supply terminal to the output. The third current source reduces the coupling of noise from the second power supply terminal to the output.

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