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41 条记录 (耗时 0.032 秒)

    Methods of fabricating integrated circuit devices including strained channel regions and related devices
    32.
    发明授权
    Methods of fabricating integrated circuit devices including strained channel regions and related devices 有权
    制造包括应变通道区域和相关器件的集成电路器件的方法

    公开(公告)号：US08084318B2

    公开(公告)日：2011-12-27

    申请号：US12763654

    申请日：2010-04-20

    申请人： Ki-chul Kim ,  Ho Lee ,  Jung-deog Lee

    发明人： Ki-chul Kim ,  Ho Lee ,  Jung-deog Lee

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/0653 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7848

    摘要： A method of fabricating an integrated circuit device includes forming first and second gate patterns on surfaces of a semiconductor substrate in PMOS and NMOS regions, respectively, of the substrate. P-type source/drain regions are epitaxially grown on opposite sides of the first gate pattern in the PMOS region to exert compressive stress on a first channel region therebetween adjacent the first gate pattern. N-type source/drain regions are epitaxially grown on opposite sides of the second gate pattern in the NMOS region to exert tensile stress on a second channel region therebetween adjacent the second gate pattern. Related devices are also discussed.

    摘要翻译： 一种制造集成电路器件的方法包括分别在衬底的PMOS和NMOS区域中的半导体衬底的表面上形成第一和第二栅极图案。 P型源极/漏极区域在PMOS区域中的第一栅极图案的相对侧上外延生长，以在邻近第一栅极图案的第一沟道区域上施加压应力。 N型源极/漏极区域在NMOS区域中的第二栅极图案的相对侧上外延生长，以在邻近第二栅极图案的第二沟道区域上施加拉伸应力。 还讨论了相关设备。

    METHODS OF FABRICATING INTEGRATED CIRCUIT DEVICES INCLUDING STRAINED CHANNEL REGIONS AND RELATED DEVICES
    33.
    发明申请
    METHODS OF FABRICATING INTEGRATED CIRCUIT DEVICES INCLUDING STRAINED CHANNEL REGIONS AND RELATED DEVICES 有权
    制作集成电路设备的方法，包括应变通道区域和相关设备

    公开(公告)号：US20100203692A1

    公开(公告)日：2010-08-12

    申请号：US12763654

    申请日：2010-04-20

    申请人： Ki-chul Kim ,  Ho Lee ,  Jung-deog Lee

    发明人： Ki-chul Kim ,  Ho Lee ,  Jung-deog Lee

    IPC分类号： H01L21/8238 ,  H01L21/04

    CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/0653 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7848

    摘要： A method of fabricating an integrated circuit device includes forming first and second gate patterns on surfaces of a semiconductor substrate in PMOS and NMOS regions, respectively, of the substrate. P-type source/drain regions are epitaxially grown on opposite sides of the first gate pattern in the PMOS region to exert compressive stress on a first channel region therebetween adjacent the first gate pattern. N-type source/drain regions are epitaxially grown on opposite sides of the second gate pattern in the NMOS region to exert tensile stress on a second channel region therebetween adjacent the second gate pattern. Related devices are also discussed.

    摘要翻译： 一种制造集成电路器件的方法包括分别在衬底的PMOS和NMOS区域中的半导体衬底的表面上形成第一和第二栅极图案。 P型源极/漏极区域在PMOS区域中的第一栅极图案的相对侧上外延生长，以在邻近第一栅极图案的第一沟道区域上施加压应力。 N型源极/漏极区域在NMOS区域中的第二栅极图案的相对侧上外延生长，以在邻近第二栅极图案的第二沟道区域上施加拉伸应力。 还讨论了相关设备。

    Non-volatile memory device and method of fabricating the same
    36.
    发明授权
    Non-volatile memory device and method of fabricating the same 有权
    非易失性存储器件及其制造方法

    公开(公告)号：US07473961B2

    公开(公告)日：2009-01-06

    申请号：US11183614

    申请日：2005-07-18

    申请人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Jin-hee Kim ,  Sang-su Kim

    发明人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Jin-hee Kim ,  Sang-su Kim

    IPC分类号： H01L29/792

    CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L29/792

    摘要： A non-volatile memory device having improved electrical characteristics and a method of fabricating the non-volatile memory device are provided. The non-volatile memory device includes a gate electrode, which is formed on a semiconductor substrate on which source and drain regions are formed, a trapping structure, which is interposed between the semiconductor substrate and the gate electrode and comprises an electron tunneling layer and a charge trapping layer, and an electron back-tunneling prevention layer, which is interposed between the gate electrode and the charge trapping layer, prevents electrons in the gate electrode from back-tunneling through the charge trapping layer, and is formed of a metal having a higher work function than the gate electrode.

    摘要翻译： 提供了具有改善的电特性的非易失性存储器件以及制造该非易失性存储器件的方法。 非易失性存储器件包括形成在其上形成有源极和漏极区域的半导体衬底上的栅电极，该栅极电极介于半导体衬底和栅电极之间，并且包括电子隧穿层和 电荷捕获层和插入在栅电极和电荷捕获层之间的电子反向穿隧防止层防止栅电极中的电子通过电荷捕获层反向隧穿，并且由具有 工作功能比栅电极高。

    Non-volatile memory device with buried control gate and method of fabricating the same
    37.
    发明授权
    Non-volatile memory device with buried control gate and method of fabricating the same 失效
    具有埋地控制栅极的非易失性存储器件及其制造方法

    公开(公告)号：US07420243B2

    公开(公告)日：2008-09-02

    申请号：US11248691

    申请日：2005-10-12

    申请人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Jin-hee Kim

    发明人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Jin-hee Kim

    IPC分类号： H01L29/788

    CPC分类号： H01L29/42352 ,  H01L21/28282 ,  H01L29/7923 ,  Y10S438/954

    摘要： In a non-volatile memory device with a buried control gate, the effective channel length of the control gate is increased to restrain punchthrough, and a region for storing charge is increased for attaining favorably large capacity. A method of fabricating the memory device includes forming the control gate within a trench formed in a semiconductor substrate, and forming charge storing regions in the semiconductor substrate on both sides of the control gate in a self-aligning manner, thereby allowing for multi-level cell operation.

    摘要翻译： 在具有埋地控制栅极的非易失性存储器件中，增加控制栅极的有效沟道长度以限制穿通，并且增加用于存储电荷的区域以获得有利的大容量。 一种制造存储器件的方法包括：在形成于半导体衬底中的沟槽内形成控制栅极，并以自对准的方式在控制栅极两侧的半导体衬底中形成电荷存储区域，从而允许多级 电池操作。

    SEMICONDUCTOR DEVICES INCLUDING MULTIPLE STRESS FILMS IN INTERFACE AREA AND METHODS OF PRODUCING THE SAME
    38.
    发明申请
    SEMICONDUCTOR DEVICES INCLUDING MULTIPLE STRESS FILMS IN INTERFACE AREA AND METHODS OF PRODUCING THE SAME 失效
    在界面中包括多个应力膜的半导体器件及其生产方法

    公开(公告)号：US20080079087A1

    公开(公告)日：2008-04-03

    申请号：US11851500

    申请日：2007-09-07

    申请人： Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

    发明人： Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

    IPC分类号： H01L29/78 ,  H01L21/8238

    CPC分类号： H01L21/823412 ,  H01L21/823807 ,  H01L27/088 ,  H01L27/092 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor substrate includes a first transistor area having a first gate electrode and first source/drain areas, a second transistor area having a second gate electrode and second source/drain areas, and an interface area provided at an interface of the first transistor area and the second transistor area and having a third gate electrode. A first stress film is on the first gate electrode and the first source/drain areas of the first transistor area and at least a portion of the third gate electrode of the interface area. A second stress film is on the second gate electrode and the second source/drain areas of the second transistor area and not overlapping the first stress film on the third gate electrode of the interface area or overlapping at least a portion of the first stress film. The second stress film overlapping at least the portion of the first stress film is thinner than the second stress film in the second transistor area. Related methods are also described.

    摘要翻译： 半导体衬底包括具有第一栅极电极和第一源极/漏极区域的第一晶体管区域，具有第二栅极电极和第二源极/漏极区域的第二晶体管区域，以及设置在第一晶体管区域和 第二晶体管区域并具有第三栅电极。 第一应力膜位于第一栅极电极和第一晶体管区域的第一源极/漏极区域和界面区域的第三栅极电极的至少一部分之间。 第二应力膜位于第二晶体管区域的第二栅极电极和第二源极/漏极区域上，并且不与界面区域的第三栅电极上的第一应力膜重叠或与第一应力膜的至少一部分重叠。 与第一应力膜的至少部分重叠的第二应力膜比第二晶体管区域中的第二应力膜更薄。 还描述了相关方法。

    Non-volatile memory device and method of fabricating the same
    40.
    发明申请
    Non-volatile memory device and method of fabricating the same 失效

    公开(公告)号：US20060027854A1

    公开(公告)日：2006-02-09

    申请号：US11200491

    申请日：2005-08-09

    申请人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Sang-su Kim ,  Jin-hee Kim ,  Byou-ree Lim

    发明人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Sang-su Kim ,  Jin-hee Kim ,  Byou-ree Lim

    IPC分类号： H01L29/76

    CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L29/792

    摘要： A non-volatile memory device having an asymmetric channel structure is provided. The non-volatile memory device includes a semiconductor substrate, a source region and a drain region which are formed in the semiconductor substrate and doped with n-type impurities, a trapping structure which includes a tunneling layer, which is disposed on a predetermined region of the semiconductor substrate and through which charge carriers are tunneled, and a charge trapping layer, which is formed on the tunneling layer and traps the tunneled charge carriers, a gate insulating layer which is formed on the trapping structure and the exposed semiconductor substrate, a gate electrode which is formed on the gate insulating layer, and a channel region which is formed between the source region and the drain region and includes a first channel region formed on a lower part of the trapping structure and a second channel region formed on a lower part of the gate insulating layer, the threshold voltage of the first channel region being lower than that of the second channel region.