-
公开(公告)号：US20070034517A1
公开(公告)日：2007-02-15
申请号：US11197009
申请日：2005-08-04
申请人： Jung-Chih Tsao , Kei-Wei Chen , Yu-Ku Lin , Chyi Chern
发明人： Jung-Chih Tsao , Kei-Wei Chen , Yu-Ku Lin , Chyi Chern
CPC分类号： C25D5/10 , C25D5/18 , C25D7/123 , H01L21/2885 , H01L21/76847 , H01L21/76877
摘要： An interconnect structure for a semiconductor device and its method of manufacture is described. The interconnect structure comprises a multi-layer structure having one or more stress-relief layers. In an embodiment, stress-relief layers are positioned between layers of electroplated copper or other conductive material. The stress-relief layer counteracts stress induced by the conductive material and helps prevent or reduce a pull-back void. For an interconnect structure using electroplated copper, the stress-relief layer may be formed by temporarily reducing the electroplating current, thereby causing a thin film of copper having a larger grain size to be formed between other layers of copper. The larger grain size typically exhibits more of a compressive stress than copper with a smaller grain size. The stress relief layer may also be formed of other materials, such as SIP-Cu, Ta, SiC, or the like.
摘要翻译： 描述了半导体器件的互连结构及其制造方法。 互连结构包括具有一个或多个应力消除层的多层结构。 在一个实施例中，应力消除层位于电镀铜或其它导电材料的层之间。 应力消除层抵消由导电材料引起的应力，并有助于防止或减少拉回空隙。 对于使用电镀铜的互连结构，可以通过暂时减少电镀电流来形成应力消除层，从而在其它铜层之间形成具有较大晶粒尺寸的铜的薄膜。 较大的晶粒尺寸通常表现出比具有较小晶粒尺寸的铜更多的压缩应力。 应力消除层也可以由其它材料形成，例如SIP-Cu，Ta，SiC等。
-
公开(公告)号：US08531036B2
公开(公告)日：2013-09-10
申请号：US13563495
申请日：2012-07-31
IPC分类号： H01L23/48
CPC分类号： H01L21/76831 , H01L21/7684
摘要： A semiconductor structure is provided and includes a dielectric layer disposed over a substrate. A first non-conductive barrier layer is formed over the dielectric layer. At least one opening is formed through the first non-conductive barrier layer and within the dielectric layer. A second non-conductive barrier layer is formed over the first non-conductive barrier layer and within the opening. At least a portion of the second non-conductive barrier layer is removed, thereby at least partially exposing a top surface of the first non-conductive barrier layer and a bottom surface of the opening, with the second non-conductive barrier layer remaining on sidewalls of the opening. A seed layer and conductive layer is disposed in the opening.
摘要翻译： 提供半导体结构，并且包括设置在基板上的电介质层。 在电介质层上形成第一非导电阻挡层。 通过第一非导电阻挡层和介电层内形成至少一个开口。 在第一非导电阻挡层上并在开口内形成第二非导电阻挡层。 去除第二非导电阻挡层的至少一部分，从而至少部分地暴露第一非导电阻挡层的顶表面和开口的底表面，而第二非导电阻挡层保留在侧壁上 的开幕。 种子层和导电层设置在开口中。
-
公开(公告)号：US20120292768A1
公开(公告)日：2012-11-22
申请号：US13563495
申请日：2012-07-31
IPC分类号： H01L23/52
CPC分类号： H01L21/76831 , H01L21/7684
摘要： A semiconductor structure is provided and includes a dielectric layer disposed over a substrate. A first non-conductive barrier layer is formed over the dielectric layer. At least one opening is formed through the first non-conductive barrier layer and within the dielectric layer. A second non-conductive barrier layer is formed over the first non-conductive barrier layer and within the opening. At least a portion of the second non-conductive barrier layer is removed, thereby at least partially exposing a top surface of the first non-conductive barrier layer and a bottom surface of the opening, with the second non-conductive barrier layer remaining on sidewalls of the opening. A seed layer and conductive layer is disposed in the opening.
摘要翻译： 提供半导体结构，并且包括设置在基板上的电介质层。 在电介质层上形成第一非导电阻挡层。 通过第一非导电阻挡层和介电层内形成至少一个开口。 在第一非导电阻挡层上并在开口内形成第二非导电阻挡层。 去除第二非导电阻挡层的至少一部分，从而至少部分地暴露第一非导电阻挡层的顶表面和开口的底表面，而第二非导电阻挡层保留在侧壁上 的开幕。 种子层和导电层设置在开口中。
-
公开(公告)号：US07969708B2
公开(公告)日：2011-06-28
申请号：US11933919
申请日：2007-11-01
申请人： Jung-Chih Tsao , Miao-Cheng Liao , Phil Sun , Kei-Wei Chen
发明人： Jung-Chih Tsao , Miao-Cheng Liao , Phil Sun , Kei-Wei Chen
IPC分类号： H01G4/06
摘要： A method for forming an alpha-tantalum layer comprising disposing a nitrogen containing base layer on a semiconductor substrate, bombarding the nitrogen containing base layer with a bombarding element, thereby forming an alpha-tantalum seed layer, and sputtering a layer of tantalum on the alpha-tantalum seed layer, thereby forming a surface layer of substantially alpha-tantalum.
摘要翻译： 一种用于形成α-钽层的方法，包括在半导体衬底上设置含氮基底层，用轰击元件轰击含氮基底层，从而形成α-钽种子层，并且在该α层上溅射一层钽 钽籽晶层，从而形成基本上为α-钽的表面层。
-
公开(公告)号：US20090116169A1
公开(公告)日：2009-05-07
申请号：US11933919
申请日：2007-11-01
申请人： Jung-Chih Tsao , Miao-Cheng Liao , Phil Sun , Kei-Wei Chen
发明人： Jung-Chih Tsao , Miao-Cheng Liao , Phil Sun , Kei-Wei Chen
摘要： A method for forming an alpha-tantalum layer comprising disposing a nitrogen containing base layer on a semiconductor substrate, bombarding the nitrogen containing base layer with a bombarding element, thereby forming an alpha-tantalum seed layer, and sputtering a layer of tantalum on the alpha-tantalum seed layer, thereby forming a surface layer of substantially alpha-tantalum.
摘要翻译： 一种用于形成α-钽层的方法，包括在半导体衬底上设置含氮基底层，用轰击元件轰击含氮基底层，从而形成α-钽种子层，并且在该α层上溅射一层钽 钽籽晶层，从而形成基本上为α-钽的表面层。
-
公开(公告)号：US20080251889A1
公开(公告)日：2008-10-16
申请号：US11733897
申请日：2007-04-11
申请人： Jung-Chih Tsao , Yu-Sheng Wang , Kei-Wei Chen , Ying-Lang Wang
发明人： Jung-Chih Tsao , Yu-Sheng Wang , Kei-Wei Chen , Ying-Lang Wang
IPC分类号： H01L29/00
CPC分类号： H01L27/0805 , H01L28/60 , H01L28/75
摘要： A semiconductor device is disclosed. The device includes a substrate, a first metal layer, a dielectric layer, and a second metal layer. The first metal layer comprises a body-centered cubic lattice metal, and overlies the substrate. The dielectric layer overlies the first metal layer. The second metal layer overlies the dielectric layer.
摘要翻译： 公开了一种半导体器件。 该器件包括衬底，第一金属层，电介质层和第二金属层。 第一金属层包括体心立方晶格金属，并且覆盖在基底上。 电介质层覆盖在第一金属层上。 第二金属层覆盖在电介质层上。
-
公开(公告)号：US20070257366A1
公开(公告)日：2007-11-08
申请号：US11416945
申请日：2006-05-03
IPC分类号： H01L21/4763
CPC分类号： H01L21/76846 , H01L21/76844 , H01L21/76865
摘要： A method for producing a semiconductor-device having an electrical interconnect. The method produces having an improved barrier layer between the interconnect conductor and the dielectric material in which the interconnect recess is formed. A dielectric layer is formed on top of a wafer substrate having at least one contact region. An interconnect for servicing the contact region is fabricated by forming an interconnect recess and then depositing a primary barrier layer of tantalum nitride and subjecting it to a re-sputtering operation. A film layer of tantalum is then deposited and re-sputtered. Following this operation, a seed layer is formed, and then a conductor is used to fill the interconnect recess. Planerizing the surface of the wafer so that further fabrication may be performed may complete the process.
摘要翻译： 一种具有电互连的半导体器件的制造方法。 该方法产生在互连导体和形成有互连凹槽的电介质材料之间具有改进的阻挡层。 在具有至少一个接触区域的晶片衬底的顶部上形成电介质层。 通过形成互连凹槽然后沉积氮化钽的主阻挡层并对其进行再溅射操作来制造用于维护接触区域的互连。 然后沉积钽薄膜层并重新溅射。 在该操作之后，形成种子层，然后使用导体来填充互连凹槽。 使晶片的表面平整化，以便进一步制造可以完成该工艺。
-
公开(公告)号：US20100230815A1
公开(公告)日：2010-09-16
申请号：US12785618
申请日：2010-05-24
申请人： Jung-Chih Tsao , Kei-Wei Chen , Yu-Ku Lin
发明人： Jung-Chih Tsao , Kei-Wei Chen , Yu-Ku Lin
IPC分类号： H01L23/522 , H01L23/48
CPC分类号： H01L23/5226 , H01L21/76805 , H01L21/76807 , H01L21/76832 , H01L21/76844 , H01L21/76846 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Semiconductor devices and methods for fabricating the same. An exemplary device includes a substrate, a dielectric layer, a protection layer, and a conformal barrier layer. The dielectric layer overlies the substrate and comprises an opening. The opening comprises a lower portion and a wider upper portion, exposing parts of the substrate. The bottoms of the upper portion act as shoulders of the opening. The protection layer overlies at least one shoulder of the opening. The conformal barrier layer is disposed in the opening and overlies the protection layer and the dielectric layer, wherein etching resistance of the protection layer against inert-gas plasma is higher than that of the barrier layer.
摘要翻译： 半导体器件及其制造方法。 示例性器件包括衬底，电介质层，保护层和共形阻挡层。 电介质层覆盖在衬底上并且包括开口。 开口包括下部和较宽的上部，暴露基底的部分。 上部的底部作为开口的肩部。 保护层覆盖开口的至少一个肩部。 共形阻挡层设置在开口中并覆盖保护层和电介质层，其中保护层对惰性气体等离子体的耐蚀性高于阻挡层的抗蚀性。
-
公开(公告)号：US07417321B2
公开(公告)日：2008-08-26
申请号：US11323484
申请日：2005-12-30
申请人： Jung-Chih Tsao , Kei-Wei Chen , Ying-Jing Lu , Yu-Sheng Wang , Yu-Ku Lin
发明人： Jung-Chih Tsao , Kei-Wei Chen , Ying-Jing Lu , Yu-Sheng Wang , Yu-Ku Lin
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76846 , H01L21/76865 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Via structure and process flow for interconnection in a semiconductor product. A bottom metal layer is provided to represent a connection layer in the semiconductor product. An isolation layer on the bottom metal layer comprises a via hole exposing a portion of the bottom metal layer. The via hole comprises a sidewall and a bottom. A first barrier metal layer is disposed on the sidewall of the via hole, but not on the bottom of the via hole. A metal under-layer is formed on the bottom of the via hole and on the first barrier metal layer. A second barrier metal layer is formed on the metal under-layer. A metal fill layer fills the via hole. A lattice mismatch between the metal under-layer and the second barrier metal layer is less than about 5%.
摘要翻译： 通过半导体产品互连的结构和工艺流程。 提供底部金属层以表示半导体产品中的连接层。 底部金属层上的隔离层包括露出底部金属层的一部分的通孔。 通孔包括侧壁和底部。 第一阻挡金属层设置在通孔的侧壁上，但不设置在通孔的底部。 在通孔的底部和第一阻挡金属层上形成金属底层。 在金属底层上形成第二阻挡金属层。 金属填充层填充通孔。 金属底层和第二阻挡金属层之间的晶格失配小于约5％。
-
公开(公告)号：US20070252277A1
公开(公告)日：2007-11-01
申请号：US11380666
申请日：2006-04-28
申请人： Jung-Chih Tsao , Kei-Wei Chen , Shih-Chieh Chang , Yu-Ku Lin , Ying-Lang Wang
发明人： Jung-Chih Tsao , Kei-Wei Chen , Shih-Chieh Chang , Yu-Ku Lin , Ying-Lang Wang
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L23/485 , H01L21/76844 , H01L21/76865 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device. The semiconductor device includes a substrate, a dielectric layer formed thereon, an opening formed in the dielectric layer, a first barrier layer overlying the sidewall of the opening, a second barrier layer overlying the first barrier layer and the bottom of the opening, and a conductive layer filled into the opening. The invention also provides a method of fabricating the semiconductor device.
摘要翻译： 半导体器件。 所述半导体器件包括：衬底，形成在其上的电介质层，形成在所述电介质层中的开口;覆盖所述开口侧壁的第一阻挡层，覆盖所述第一阻挡层和所述开口底部的第二势垒层;以及 导电层填充入开口。 本发明还提供一种制造半导体器件的方法。
-
-
-
-
-
-
-
-
-
搜索结果
40 条记录 (耗时 0.05 秒)
