公开(公告)号：US20050017287A1

公开(公告)日：2005-01-27

申请号：US10623912

申请日：2003-07-21

申请人： Yue-Der Chih ,  Chrong-Jung Lin ,  Sheng-Wei Tsao ,  Chin-Huang Wang

发明人： Yue-Der Chih ,  Chrong-Jung Lin ,  Sheng-Wei Tsao ,  Chin-Huang Wang

IPC分类号： G11C16/04 ,  H01L27/115 ,  H01L33/00

CPC分类号： G11C16/0433 ,  H01L27/115

摘要： This invention provides a memory array and it support signals and a method for byte access for programming, erasing and reading memory cells. The advantage of this array and method is the ability to access bytes for program, erase, and read operations. This array and method uses an added isolation transistor to isolate the high voltage from the unselected byte. In addition, it utilizes a separate source line for each byte in a row. This source line is also shared by a byte in a different row. The array has very little peripheral circuit overhead requirement and it avoids programming disturbances of unselected memory cells.

摘要翻译： 本发明提供了一种存储器阵列，并且它支持信号和用于编程，擦除和读取存储器单元的字节访问的方法。 该数组和方法的优点是可以访问字节进行程序，擦除和读取操作。 该阵列和方法使用添加的隔离晶体管将高电压与未选择的字节隔离开来。 此外，它为一行中的每个字节使用单独的源行。 该源行也由不同行中的一个字节共享。 阵列具有非常少的外围电路开销要求，并且避免了未选择的存储单元的编程干扰。

公开(公告)号：US20050007824A1

公开(公告)日：2005-01-13

申请号：US10858020

申请日：2004-06-01

申请人： Yue-Der Chih

发明人： Yue-Der Chih

IPC分类号： G11C11/22 ,  G11C16/04 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/792

CPC分类号： G11C16/0425 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/792

摘要： An nonvolatile memory device having improved endurance is comprised of an array of nonvolatile memory cells arranged in rows and columns. Each memory cell is composed of a program transistor and read transistor with a control gate connected to a word line, a source connected the source select line, and a floating gate onto which an electronic charge is placed representing a data bit stored within the nonvolatile memory device. The program transistor has a drain connected a first bit line and a read transistor has a drain connected to the second bit line. Each memory cell has a floating gate connector joining the floating gate of the read transistor to the floating gate of the read transistor. The nonvolatile memory device has a voltage controller that programs the each memory cell by programming the program transistor and reading the read transistor.

摘要翻译： 具有改进的耐久性的非易失性存储器件包括以行和列布置的非易失性存储单元的阵列。 每个存储单元由程序晶体管和读取晶体管组成，其中控制栅极连接到字线，连接源选择线的源和放置有电子电荷的浮置栅极表示存储在非易失性存储器内的数据位 设备。 程序晶体管的漏极与第一位线连接，而读取晶体管的漏极连接到第二位线。 每个存储单元具有将读取晶体管的浮置栅极连接到读出晶体管的浮动栅极的浮动栅极连接器。 非易失性存储器件具有电压控制器，其通过对程序晶体管进行编程并读取读取晶体管来对每个存储单元进行编程。

公开(公告)号：US06808985B1

公开(公告)日：2004-10-26

申请号：US10082021

申请日：2002-02-21

申请人： Kuei-Ying Lee ,  Shao-Yu Chou ,  Jiun-Nan Chen ,  Yue-Der Chih ,  Sam Sheng-Deh Chu ,  Feng-Ming Kuo

发明人： Kuei-Ying Lee ,  Shao-Yu Chou ,  Jiun-Nan Chen ,  Yue-Der Chih ,  Sam Sheng-Deh Chu ,  Feng-Ming Kuo

IPC分类号： H01L2100

CPC分类号： H01L27/11526 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/112 ,  H01L27/1126 ,  H01L27/11293 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11546

摘要： A method of fabricating ROM products through the use of embedded flash/EEPROM prototypes is disclosed. This is accomplished by first forming a Flash/EEPROM prototype, performing programming simulations on the prototype, developing a ROM code and mask, and then forming a ROM product in the same manufacturing line by skipping certain Flash/EEPROM steps and then implanting the ROM code into the final ROM product. The method improves turn-around-time in the manufacturing line, and reduces cost to the customer. A method of doing business is also disclosed directed to providing ROM products to a customer without much redesign time and effort on the part of the customer.

摘要翻译： 公开了通过使用嵌入式闪存/ EEPROM原型来制造ROM产品的方法。 这是通过首先形成闪存/ EEPROM原型，对原型进行编程仿真，开发ROM代码和掩码，然后通过跳过某些闪存/ EEPROM步骤在同一生产线上形成ROM产品，然后植入ROM代码 进入最终的ROM产品。 该方法提高了生产线的周转时间，降低了客户的成本。 还公开了一种开展业务的方法，其目的是向客户提供ROM产品，而不需要客户的重新设计时间和精力。

公开(公告)号：US08754498B2

公开(公告)日：2014-06-17

申请号：US12606497

申请日：2009-10-27

申请人： Yue-Der Chih ,  Chrong Jung Lin

发明人： Yue-Der Chih ,  Chrong Jung Lin

IPC分类号： H01L29/86

CPC分类号： H01L23/5252 ,  H01L27/112 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of making an antifuse includes providing a substrate having a bit line diffusion region and a capacitor diffusion region. A gate dielectric layer is formed over the substrate, and a word line is formed on the gate dielectric layer. An oxide layer is formed on the capacitor diffusion region, in a separate process step from forming the gate dielectric layer. A select line contact is formed above and contacting the oxide layer to form a capacitor having the oxide layer as a capacitor dielectric layer of the capacitor. The select line contact is configured for applying a voltage to cause permanent breakdown of the oxide layer to program the antifuse.

摘要翻译： 制造反熔丝的方法包括提供具有位线扩散区域和电容器扩散区域的衬底。 栅极电介质层形成在衬底上，并且在栅极电介质层上形成字线。 在形成栅极电介质层的分离工艺步骤中，在电容器扩散区上形成氧化物层。 在上方形成选择线接触并与氧化物层接触以形成具有作为电容器的电容器电介质层的氧化物层的电容器。 选择线触点被配置为施加电压以导致氧化物层的永久性击穿来编程反熔丝。

公开(公告)号：US08687412B2

公开(公告)日：2014-04-01

申请号：US13438006

申请日：2012-04-03

申请人： Yue-Der Chih ,  Chun-Jung Lin ,  Kai-Chun Lin ,  Hung-Chang Yu

发明人： Yue-Der Chih ,  Chun-Jung Lin ,  Kai-Chun Lin ,  Hung-Chang Yu

IPC分类号： G11C11/00

CPC分类号： G11C11/161 ,  G11C11/1673

摘要： A reference circuit discerns high or low resistance states of a magneto-resistive memory element such as a bit cell. The reference circuit has magnetic tunnel junction (MTJ) elements in complementary high and low resistance states RH and RL, providing a voltage, current or other parameter for comparison against the memory element to discern a resistance state. The parameter represents an intermediate resistance straddled by RH and RL, such as an average or twice-parallel resistance. The reference MTJ elements are biased from the same read current source as the memory element but their magnetic layers are in opposite order, physically or by order along bias current paths. The reference MTJ elements are biased to preclude any read disturb risk. The memory bit cell is coupled to the same bias polarity source along a comparable path, being safe from read disturb risk in one of its two possible logic states.

摘要翻译： 参考电路识别诸如位单元的磁阻存储元件的高或低电阻状态。 参考电路具有互补的高电阻状态RH和低电阻状态RL的磁隧道结（MTJ）元件，提供用于与存储元件进行比较的电压，电流或其它参数以识别电阻状态。 该参数表示由RH和RL跨过的中间电阻，例如平均或两倍平行的电阻。 参考MTJ元件从与存储元件相同的读取电流源偏置，但它们的磁性层在物理上或沿着偏置电流路径的顺序是相反的顺序。 参考MTJ元件被偏置以排除任何读取干扰风险。 存储器位单元沿着可比较的路径耦合到相同的偏置极性源，在其两种可能的逻辑状态之一中可以避免读取干扰风险。

公开(公告)号：US08674751B2

公开(公告)日：2014-03-18

申请号：US13447594

申请日：2012-04-16

申请人： Justin Shi ,  Yue-Der Chih

发明人： Justin Shi ,  Yue-Der Chih

IPC分类号： G05F1/10 ,  G05F3/02

CPC分类号： G11C5/147 ,  G11C16/30

摘要： A method for generating a reference voltage in an integrated circuit device that is powered by a low voltage power includes generating a coarse first reference voltage using a coarse reference generator, routing the coarse first reference voltage to a boost regulator as an input reference voltage by a hand-off switch circuit, the boost regulator generating an initial-state stepped-up supply based on the first reference voltage, and generating at least two outputs of a second, more accurate, reference voltage from the stepped-up supply voltage using a fine-resolution reference generator. The second reference can be then looped back to the boost regulator, thus, generating a more accurate steady-state stepped-up supply voltage.

摘要翻译： 在由低电压电力供电的集成电路器件中产生参考电压的方法包括：使用粗略参考发生器产生粗略的第一参考电压，将粗略的第一参考电压作为输入参考电压布置为升压调节器， 切换开关电路，所述升压调节器基于所述第一参考电压产生初始状态升压电源，以及使用罚款从所述升压电源电压产生第二更准确的参考电压的至少两个输出 分辨率参考发生器。 然后可以将第二参考信号环回到升压调节器，从而产生更准确的稳态升压电源电压。

公开(公告)号：US08325521B2

公开(公告)日：2012-12-04

申请号：US12900608

申请日：2010-10-08

申请人： Chia-Ta Hsieh ,  Yue-Der Chih

发明人： Chia-Ta Hsieh ,  Yue-Der Chih

IPC分类号： G11C16/26

CPC分类号： G11C16/08 ,  G11C16/26 ,  G11C16/3418

摘要： A method of performing a reading operation to a memory device including a plurality of flash memory cells. The method includes applying a first voltage bias to a control gate of a selected memory cell in the flash memory array and applying a second voltage bias to a word line of the selected memory cell. A control gate of an unselected memory cell in the flash memory array is grounded and a third voltage bias is applied to a word line of the unselected cell to turn off a word line channel of the unselected memory cell. The selected memory cell and unselected memory cell are configured in the memory device and are connected to different word lines. The first voltage bias and the second voltage bias have a same polarity. The third voltage bias and the second voltage bias have opposite polarities.

摘要翻译： 一种对包括多个闪存单元的存储器件执行读取操作的方法。 该方法包括将第一电压偏压施加到闪速存储器阵列中所选存储单元的控制栅极，并将第二电压偏压施加到所选存储单元的字线。 闪速存储器阵列中的未选择存储单元的控制栅极接地，并且第三电压偏压被施加到未选择单元的字线以关闭未选择的存储单元的字线通道。 选择的存储单元和未选择的存储单元被配置在存储器件中并被连接到不同的字线。 第一电压偏置和第二电压偏置具有相同的极性。 第三电压偏置和第二电压偏置具有相反的极性。

公开(公告)号：US08238178B2

公开(公告)日：2012-08-07

申请号：US12704676

申请日：2010-02-12

申请人： Tien-Chun Yang ,  Yue-Der Chih ,  Shang-Hsuan Liu

发明人： Tien-Chun Yang ,  Yue-Der Chih ,  Shang-Hsuan Liu

IPC分类号： G11C7/00 ,  G11C11/34

CPC分类号： G11C29/04 ,  G11C16/0408 ,  G11C16/0483 ,  G11C29/808

摘要： A memory circuit includes a first group of memory arrays including a first memory array coupled with a first input/output (IO) interface and a second memory array coupled with a second IO interface. A second group of memory arrays include a third memory array coupled with a third IO interface and a fourth memory array coupled with a fourth TO interface. A plurality of redundancy bit lines include at least one first redundancy bit line that is configured for selectively repairing the first group of memory arrays, and at least one second redundancy bit line that is configured for selectively repairing the second group of memory arrays.

摘要翻译： 存储器电路包括第一组存储器阵列，其包括与第一输入/输出（IO）接口耦合的第一存储器阵列和与第二IO接口耦合的第二存储器阵列。 第二组存储器阵列包括与第三IO接口耦合的第三存储器阵列和与第四TO接口耦合的第四存储器阵列。 多个冗余位线包括被配置用于选择性地修复第一组存储器阵列的至少一个第一冗余位线和被配置用于选择性地修复第二组存储器阵列的至少一个第二冗余位线。

公开(公告)号：US20120163086A1

公开(公告)日：2012-06-28

申请号：US12979425

申请日：2010-12-28

申请人： Tien-Chung Yang ,  Chia-Fu Lee ,  Yue-Der Chih

发明人： Tien-Chung Yang ,  Chia-Fu Lee ,  Yue-Der Chih

IPC分类号： G11C16/08

CPC分类号： G11C16/06 ,  G11C16/30 ,  G11C2216/22

摘要： A device comprises an address storage device. A first circuit includes a first flash memory, configured to sequentially receive first and second addresses and store the first address in the address storage device. The first circuit has a first set of control inputs for causing the first circuit to perform a first operation from the group consisting of read, program and erase on a cell of the first flash memory corresponding to a selected one of the first and second addresses. A second circuit includes a second flash memory, configured to receive the second address. The second circuit has a second set of control inputs for causing the second circuit to read data from a cell of the second flash memory corresponding to the second address while the first operation is being performed.

摘要翻译： 设备包括地址存储设备。 第一电路包括第一闪存，其被配置为顺序地接收第一和第二地址并将第一地址存储在地址存储设备中。 第一电路具有第一组控制输入，用于使第一电路从与第一和第二地址中的所选择的一个对应的第一闪存的单元上的读取，编程和擦除组合执行第一操作。 第二电路包括被配置为接收第二地址的第二闪存。 第二电路具有第二组控制输入，用于在执行第一操作时使第二电路从对应于第二地址的第二闪速存储器的单元读取数据。

公开(公告)号：US20110199845A1

公开(公告)日：2011-08-18

申请号：US12704676

申请日：2010-02-12

申请人： Tien-Chun YANG ,  Yue-Der Chih ,  Shang-Hsuan Liu

发明人： Tien-Chun YANG ,  Yue-Der Chih ,  Shang-Hsuan Liu

IPC分类号： G11C29/00

CPC分类号： G11C29/04 ,  G11C16/0408 ,  G11C16/0483 ,  G11C29/808

摘要： A memory circuit includes a first group of memory arrays including a first memory array coupled with a first input/output (IO) interface and a second memory array coupled with a second IO interface. A second group of memory arrays include a third memory array coupled with a third input/output (IO) interface and a fourth memory array coupled with a fourth IO interface. A plurality of redundancy bit lines include at least one first redundancy bit line that is configured for selectively repairing the first group of memory arrays, and at least one second redundancy bit line that is configured for selectively repairing the second group of memory arrays.

摘要翻译： 存储器电路包括第一组存储器阵列，其包括与第一输入/输出（IO）接口耦合的第一存储器阵列和与第二IO接口耦合的第二存储器阵列。 第二组存储器阵列包括与第三输入/输出（IO）接口耦合的第三存储器阵列和与第四IO接口耦合的第四存储器阵列。 多个冗余位线包括被配置用于选择性地修复第一组存储器阵列的至少一个第一冗余位线和被配置用于选择性地修复第二组存储器阵列的至少一个第二冗余位线。