公开(公告)号：US20200279941A1

公开(公告)日：2020-09-03

申请号：US16650834

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Cheng-Ying HUANG ,  Willy RACHMADY ,  Gilbert DEWEY ,  Erica J. THOMPSON ,  Aaron D. LILAK ,  Jack T. KAVALIEROS

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/165

Abstract: Disclosed are etchstop regions in fins of semiconductor devices, and related methods. A semiconductor device includes a buried region, a fin on the buried region, and a gate formed at least partially around the fin. At least a portion of the fin that borders the buried region includes an etchstop material. The etchstop material includes a doped semiconductor material that has a slower etch rate than that of an intrinsic form of the semiconductor material. A method of manufacturing a semiconductor device includes forming a gate on a fin, implanting part of the fin with dopants configured to decrease an etch rate of the part of the fin, removing at least part of the fin, and forming an epitaxial semiconductor material on a remaining proximal portion of the fin.

公开(公告)号：US20190172950A1

公开(公告)日：2019-06-06

申请号：US16323661

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Sean T. MA ,  Rishabh MEHANDRU ,  Patrick MORROW ,  Stephen M. CEA

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/762 ,  H01L29/66

Abstract: An integrated circuit apparatus including a body; a transistor formed on a first portion of the body, the transistor including a gate stack and a channel defined in the body between a source and a drain; and a plug formed in a second portion of the body, the plug including a material operable to impart a stress on the first portion of the body. A method of forming an integrated circuit device including forming a transistor body on a substrate; forming a transistor device in a first portion of the transistor body on a first side of the substrate; and dividing the transistor body into at least the first portion and a second portion with a plug in the transistor body, the plug including a material operable to impart a stress on the first portion of the body, wherein the material is introduced through a second side of the substrate.

公开(公告)号：US20180315838A1

公开(公告)日：2018-11-01

申请号：US15770463

申请日：2015-12-18

Applicant: Intel Corporation

Inventor： Patrick MORROW ,  Rishabh MEHANDRU ,  Aaron D. LILAK

IPC: H01L29/66 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092

CPC classification number: H01L29/66439 ,  H01L21/8221 ,  H01L21/823475 ,  H01L21/823842 ,  H01L21/823871 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0673

Abstract: A first interconnect layer is bonded to a first substrate. The first interconnect layer is deposited on a first device layer on a second device layer on a second substrate. The second device layer is revealed from the second substrate side. A first insulating layer is deposited on the revealed second device layer. A first opening is formed in the first insulating layer to expose a first portion of the second device layer. A contact region is formed on the exposed first portion of the second device layer.

公开(公告)号：US20180248005A1

公开(公告)日：2018-08-30

申请号：US15774952

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Stephen M. CEA ,  Rishabh MEHANDRU ,  Cory E. WEBER

IPC: H01L29/10 ,  H01L29/167 ,  H01L29/78 ,  H01L21/304 ,  H01L21/306 ,  H01L21/265 ,  H01L21/324 ,  H01L29/66

CPC classification number: H01L29/1083 ,  H01L21/26513 ,  H01L21/26566 ,  H01L21/304 ,  H01L21/30625 ,  H01L21/324 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: Methods for doping a sub-fin region of a semiconductor structure include providing a semiconductor structure that comprises a substrate and a plurality of fins formed on the substrate, the plurality of fins having sub-fin regions adjacent to the substrate; removing the substrate to expose a portion of the sub-fin regions of the plurality of fins, and implanting a dopant material into the exposed portion of the sub-fin region. The method may also include performing an annealing process after the implantation such that the dopant becomes electrically active. The method may also include patterning the backside of the semiconductor structure. Devices constructed using the disclosed methods are also provided, and other embodiments are discussed.

公开(公告)号：US20170162676A1

公开(公告)日：2017-06-08

申请号：US15434981

申请日：2017-02-16

Applicant: Intel Corporation

Inventor： Annalisa CAPPELLANI ,  Stephen M. CEA ,  Tahir GHANI ,  Harry GOMEZ ,  Jack T. KAVALIEROS ,  Patrick H. KEYS ,  Seiyon KIM ,  Kelin J. KUHN ,  Aaron D. LILAK ,  Rafael RIOS ,  Mayank SAHNI

IPC: H01L29/66 ,  H01L21/762 ,  H01L29/423 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/66818 ,  B82Y10/00 ,  H01L21/762 ,  H01L21/76216 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: Semiconductor devices with isolated body portions are described. For example, a semiconductor structure includes a semiconductor body disposed above a semiconductor substrate. The semiconductor body includes a channel region and a pair of source and drain regions on either side of the channel region. An isolation pedestal is disposed between the semiconductor body and the semiconductor substrate. A gate electrode stack at least partially surrounds a portion of the channel region of the semiconductor body.