METHODS AND APPARATUS TO INCREASE RESILIENCY IN SELF-HEALING MECHANISMS

    公开(公告)号:US20220012129A1

    公开(公告)日:2022-01-13

    申请号:US17484951

    申请日:2021-09-24

    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to increase resiliency in self-healing mechanisms. At least one non-transitory machine-readable medium comprises instructions that, when executed, cause at least one processor to at least partition computational resources of a first host into a primary partition and a shadow partition, the primary partition to communicate with a second host, apply a fix for the primary partition, determine if the primary partition can communicate with the second host during the application of the fix, cause, in response to the determination that the primary partition cannot communicate with the second host during the application of the fix, the shadow partition to communicate with the second host; and transfer communication with the second host from the shadow partition to the primary partition, the transfer in response to a determination that the application of the fix is complete.

    Licensing in the cloud
    36.
    发明授权

    公开(公告)号:US10289814B2

    公开(公告)日:2019-05-14

    申请号:US14581742

    申请日:2014-12-23

    Abstract: At least one machine readable medium comprising a plurality of instructions that in response to being executed by a system cause the system to send a unique identifier to a license server, establish a secure channel based on the unique identifier, request a license for activating an appliance from a license server over the secure channel, receive license data from the license server over the secure channel; determine whether the license is valid, and activate the appliance in response to a determination that the license data is valid.

    Power gating a portion of a cache memory
    40.
    发明授权
    Power gating a portion of a cache memory 有权
    电源选通高速缓存的一部分

    公开(公告)号:US09176875B2

    公开(公告)日:2015-11-03

    申请号:US13785228

    申请日:2013-03-05

    Abstract: In an embodiment, a processor includes multiple tiles, each including a core and a tile cache hierarchy. This tile cache hierarchy includes a first level cache, a mid-level cache (MLC) and a last level cache (LLC), and each of these caches is private to the tile. A controller coupled to the tiles includes a cache power control logic to receive utilization information regarding the core and the tile cache hierarchy of a tile and to cause the LLC of the tile to be independently power gated, based at least in part on this information. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中,处理器包括多个瓦片,每个瓦片包括核心和瓦片高速缓存层级。 该瓦片高速缓存层级包括第一级高速缓存,中级缓存(MLC)和最后级高速缓存(LLC),并且这些高速缓存中的每一个对于该瓦片是私有的。 耦合到瓦片的控制器包括高速缓存功率控制逻辑,用于至少部分地基于该信息来接收关于瓦片的核心和瓦片高速缓存层级的利用信息,并且使瓦片的LLC独立地进行电源门控。 描述和要求保护其他实施例。

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