公开(公告)号：US20190334010A1

公开(公告)日：2019-10-31

申请号：US15751104

申请日：2015-09-11

Applicant: Intel Corporation

Inventor： Uygar E. Avci ,  Daniel H. Morris ,  Ian A. Young

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L27/11585

Abstract: Described is an apparatus which comprises a transistor including: a layer of ferroelectric material; a layer of insulating material; and an oxide layer or a metal layer sandwiched between the layer of ferroelectric material and the layer of insulating material, wherein thickness of the ferroelectric material is less than thickness of the layer of insulating material; and a driver coupled to the transistor. Described is an apparatus which comprises: a transistor including: a first oxide layer of High-K material; a second oxide layer; and a layer of nanocrystals sandwiched between the first and second oxide layers, wherein thickness of first oxide layer is greater than thickness of the second oxide layer; and a driver coupled to the transistor.

公开(公告)号：US20190273087A1

公开(公告)日：2019-09-05

申请号：US16347085

申请日：2016-12-12

Applicant: Intel Corporation

Inventor： Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young

IPC: H01L27/1159 ,  G11C11/22 ,  H01L29/78

Abstract: Described herein are ferroelectric memory cells and corresponding methods and devices. For example, in some embodiments, a ferroelectric memory cell disclosed herein includes one access transistor and one ferroelectric transistor (1T-1FE-FET cell). The access transistor is coupled to the ferroelectric transistor by sharing its source/drain terminal with that of the ferroelectric transistor and is used for both READ and WRITE access to the ferroelectric transistor.

公开(公告)号：US10355005B2

公开(公告)日：2019-07-16

申请号：US15576269

申请日：2015-06-26

Applicant: INTEL CORPORATION

Inventor： Uygar E. Avci ,  Daniel H. Morris ,  Ian A. Young ,  Stephen M. Ramey

IPC: H01L27/11521 ,  G11C16/04 ,  H01L21/28 ,  H01L29/49 ,  H01L29/78 ,  H01L29/788 ,  H01L27/11519 ,  H01L27/11558 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L27/11526 ,  H01L29/66 ,  H01L21/762 ,  H01L27/02 ,  H01L29/06

Abstract: Embodiments of the present disclosure provide techniques and configurations for semi-volatile embedded memory with between-fin floating gates. In one embodiment, an apparatus includes a semiconductor substrate and a floating-gate memory structure formed on the semiconductor substrate including a bitcell having first, second, and third fin structures extending from the substrate, an oxide layer disposed between the first and second fin structures and between the second and third fin structures, a gate of a first transistor disposed on the oxide layer and coupled with and extending over a top of the first fin structure, and a floating gate of a second transistor disposed on the oxide layer between the second and third fin structures. Other embodiments may be described and/or claimed.

公开(公告)号：US20170018304A1

公开(公告)日：2017-01-19

申请号：US15282484

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Daniel H. Morris ,  Uygar E. Avci ,  Rafael Rios ,  Ian A. Young

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C5/145 ,  G11C11/412 ,  H01L27/1104 ,  H03K3/356104

Abstract: Embodiments include apparatuses, methods, and systems for a circuit to shift a voltage level. The circuit may include a first inverter that includes a first transistor coupled to pass a low voltage signal and a second inverter coupled to receive the low voltage signal. The circuit may further include a second transistor coupled to receive the low voltage signal from the second inverter to serve as a feedback device and produce a high voltage signal. In embodiments, the first transistor conducts asymmetrically to prevent crossover of the high voltage signal into the low voltage domain. A low voltage memory array is also described. In embodiments, the circuit to shift a voltage level may assist communication between a logic component including the low voltage memory array of a low voltage domain and a logic component of a high voltage domain. Additional embodiments may also be described.

Abstract translation: 实施例包括用于移位电压电平的电路的装置，方法和系统。 电路可以包括第一反相器，其包括耦合以传递低电压信号的第一晶体管和耦合以接收低电压信号的第二反相器。 电路还可以包括第二晶体管，其被耦合以从第二反相器接收低电压信号，以用作反馈装置并产生高电压信号。 在实施例中，第一晶体管不对称地导通，以防止高电压信号到低电压域的交叉。 还描述了低电压存储器阵列。 在实施例中，用于移位电压电平的电路可以有助于包括低电压域的低电压存储器阵列的逻辑部件与高电压域的逻辑部件之间的通信。 还可以描述另外的实施例。

公开(公告)号：US11495596B2

公开(公告)日：2022-11-08

申请号：US16147512

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Uygar E. Avci ,  Daniel H. Morris ,  Ian A. Young

IPC: H01L27/06 ,  H01L27/07 ,  H01L25/18 ,  H01L29/51 ,  H01L27/02 ,  H01L29/88 ,  H01L27/11519

Abstract: An integrated circuit structure comprises a substrate having a memory region of and an adjacent logic region. A first N type well (Nwell) is formed in the substrate for the memory region and a second Nwell formed in the substrate for the logic region. A plurality of memory transistors in the memory region and a plurality of logic transistors are in the logic region, wherein ones the memory transistors include a floating gate over a channel, and a source and a drain on opposite sides of the channel. A diode portion is formed over one of the source and the drain of at least one of the memory transistors to conduct charge to the floating-gate of the at least one of the memory transistors for state retention during power gating.

公开(公告)号：US11037614B2

公开(公告)日：2021-06-15

申请号：US16615780

申请日：2018-07-23

Applicant: Intel Corporation

Inventor： Huichu Liu ,  Sasikanth Manipatruni ,  Ian A. Young ,  Tanay Karnik ,  Daniel H. Morris ,  Kaushik Vaidyanathan

IPC: G11C11/22 ,  H01L27/11507 ,  H01L49/02

Abstract: Described is an apparatus to reduce or eliminate imprint charge, wherein the apparatus which comprises: a source line; a bit-line; a memory bit-cell coupled to the source line and the bit-line; a first multiplexer coupled to the bit-line; a second multiplexer coupled to the source-line; a first driver coupled to the first multiplexer; a second driver coupled to the second multiplexer; and a current source coupled to the first and second drivers.

公开(公告)号：US11004868B2

公开(公告)日：2021-05-11

申请号：US16487417

申请日：2017-03-22

Applicant: Intel Corporation

Inventor： Seiyon Kim ,  Uygar E. Avci ,  Joshua M. Howard ,  Ian A. Young ,  Daniel H. Morris

IPC: H01L29/78 ,  H01L27/1159 ,  H01L21/28 ,  H01L27/11592 ,  H01L29/51

Abstract: Memory field-effect transistors and methods of manufacturing the same are disclosed. An example apparatus includes a semiconductor substrate and a ferroelectric gate insulator of a memory field-effect transistor formed within a trench having walls defined by spacers and a base defined by the semiconductor substrate. The apparatus further includes a gate conductor formed on the ferroelectric gate insulator. The ferroelectric gate insulator is to separate a bottom surface of the gate conductor and the substrate.

公开(公告)号：US10901486B2

公开(公告)日：2021-01-26

申请号：US16384715

申请日：2019-04-15

Applicant: Intel Corporation

Inventor： Kaushik Vaidyanathan ,  Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young ,  Tanay Karnik ,  Huichu Liu

IPC: G06F1/3234 ,  G06F13/40 ,  G06F1/3296 ,  G06F1/324 ,  H03K19/0185

Abstract: Described is an apparatus which comprises: a first electrical path comprising at least one driver and receiver; and a second electrical path comprising at least one driver and receiver, wherein the first and second electrical paths are to receive a same input signal, wherein the first electrical path and the second electrical path are parallel to one another and have substantially the same propagation delays, and wherein the second electrical path is enabled during a first operation mode and disabled during a second operation mode.

公开(公告)号：US10720504B2

公开(公告)日：2020-07-21

申请号：US15751104

申请日：2015-09-11

Applicant: Intel Corporation

Inventor： Uygar E. Avci ,  Daniel H. Morris ,  Ian A. Young

IPC: H01L29/51 ,  H01L29/78 ,  H01L27/11585 ,  H01L29/66

Abstract: Described is an apparatus which comprises a transistor including: a layer of ferroelectric material; a layer of insulating material; and an oxide layer or a metal layer sandwiched between the layer of ferroelectric material and the layer of insulating material, wherein thickness of the ferroelectric material is less than thickness of the layer of insulating material; and a driver coupled to the transistor. Described is an apparatus which comprises: a transistor including: a first oxide layer of High-K material; a second oxide layer; and a layer of nanocrystals sandwiched between the first and second oxide layers, wherein thickness of first oxide layer is greater than thickness of the second oxide layer; and a driver coupled to the transistor.

公开(公告)号：US10707846B2

公开(公告)日：2020-07-07

申请号：US15992080

申请日：2018-05-29

Applicant: Intel Corporation

Inventor： Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young

IPC: H03K3/356 ,  H03K3/3562 ,  H01L29/66 ,  H03K3/012

Abstract: Described is an apparatus which comprises: a first p-type Tunneling Field-Effect Transistor (TFET); a first n-type TFET coupled in series with the first p-type TFET; a first node coupled to gate terminals of the first p-type and n-type TFETs; a first clock node coupled to a source terminal of the first TFET, the first clock node is to provide a first clock; and a second clock node coupled to a source terminal of the second TFET, the second clock node is to provide a second clock.