公开(公告)号：US20220300048A1

公开(公告)日：2022-09-22

申请号：US17712010

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Min Suet Lim ,  Jeff Ku ,  Fern Nee Tan ,  John Lang ,  Kavitha Nagarajan ,  Javed Shaikh ,  Deepak Sekar

IPC: G06F1/20 ,  G06F1/16 ,  H01L23/373 ,  H05K1/02 ,  H05K7/20

Abstract: Thermal Management Systems for electronic devices and related methods are disclosed. An example electronic housing includes a housing defining a cavity, electronics in the cavity, and a touch display over the electronics. A heat spreader has a first surface toward the electronics and a second surface opposite the first surface toward the touch display, where the heat spreader is to dissipate heat generated by the electronics. A glass cover is coupled to the housing and has a first side toward the touch display and a second side opposite the first side, where the glass cover is exposed external to the housing. An insulation layer is between the second surface of the heat spreader and the second side of the glass cover to restrict heat transfer from the electronics to the second side of the glass cover.

公开(公告)号：US20220225530A1

公开(公告)日：2022-07-14

申请号：US17699513

申请日：2022-03-21

Applicant: Intel Corporation

Inventor： Jeff Ku ,  Tongyan Zhai ,  Lance Lin ,  Min Suet Lim ,  Twan Sing Loo

IPC: H05K7/20 ,  H05K1/02 ,  G06F1/20

Abstract: Particular embodiments described herein provide for an electronic device that can be configured to include a support structure that includes a first side and an opposite second side. A first air mover can be coupled to the first side of the support structure, where a motor of the first air mover is on the support structure and an air mover controller where the air mover controller controls the first air mover through trace in the support structure. In some examples, a second air mover can be located on the second side of the support structure, where a motor of the second air mover is on the second side of the support structure and the second air mover is controlled by the air mover controller through trace in the support structure. The support structure can be a printed circuit board or motherboard.

公开(公告)号：US20220181289A1

公开(公告)日：2022-06-09

申请号：US17113410

申请日：2020-12-07

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Kyle Davidson ,  Min Suet Lim ,  Kevin Byrd ,  James Wade

IPC: H01L23/00 ,  H01L23/13 ,  H01L23/498 ,  H01L23/64 ,  H01L21/56

Abstract: An integrated circuit package may be fabricated by disposing an underfill material between an electronic substrate and an integrated circuit device through an opening in the electronic substrate. In one embodiment, an integrated circuit assembly may include an electronic substrate having a first surface and an opposing second surface, wherein the electronic substrate includes at least one opening extending from the first surface to the second surface. The integrated circuit assembly may further include an integrated circuit device, wherein the integrated circuit device is electrically attached to the electronic substrate with at least one interconnect, and an underfill material may be disposed between the first surface of the electronic substrate and the integrated circuit device, wherein a portion of the underfill material extends into the opening in the electronic substrate.

公开(公告)号：US20220181227A1

公开(公告)日：2022-06-09

申请号：US17677843

申请日：2022-02-22

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Jiun Hann Sir ,  Min Suet Lim ,  Richard C. Stamey ,  Chu Aun Lim ,  Jimin Yao

IPC: H01L23/31 ,  H01L23/528 ,  H01L23/538 ,  H01L23/00

Abstract: A semiconductor package is disclosed, which comprises a substrate, one or more dies on a first side of the substrate, and a plurality of interconnect structures having a first pitch and coupled to a second side of the substrate. The interconnect structures may attach the substrate to a board. The substrate may include a first interconnect layer having a second pitch. The first interconnect layer may be coupled to the one or more dies through second one or more interconnect layers. Third one or more interconnect layers between the first interconnect layer and the interconnect structures may translate the first pitch to the second pitch. The substrate may include a recess on a section of the second side of the substrate. The semiconductor package may further include one or more components within the recess and attached to the second side of the substrate.

公开(公告)号：US20220110229A1

公开(公告)日：2022-04-07

申请号：US17554814

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Boon Ping Koh ,  Yew San Lim ,  Min Suet Lim

IPC: H05K9/00

Abstract: Particular embodiments described herein provide for an electronic device that includes an electronic component, a support structure that includes a radiation source, a radiation shield on the support structure. The radiation shield includes a wall and the wall is not continuous around the radiation source and includes a radiation shield gap, where the electronic component covers the radiation shield gap to complete the radiation shield wall.

公开(公告)号：US11289414B2

公开(公告)日：2022-03-29

申请号：US16098407

申请日：2017-05-16

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Jiun Hann Sir ,  Min Suet Lim

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/50 ,  H01L23/00 ,  H01L21/48

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing a Pad on Solder Mask (PoSM) semiconductor substrate package. For instance, in accordance with one embodiment, there is a substrate package having embodied therein a functional silicon die at a top layer of the substrate package; a solder resist layer beneath the functional silicon die of the substrate package; a plurality of die bumps at a bottom surface of the functional silicon die, the plurality of die bumps electrically interfacing the functional silicon die to a substrate through a plurality of solder balls at a top surface of the solder resist layer; each of the plurality of die bumps electrically interfaced to a nickel pad at least partially within the solder resist layer and beneath the solder balls; each of the plurality of die bumps electrically interfaced through the nickel pads to a conductive pad exposed at a bottom surface of the solder resist layer; and in which each of the conductive pads exposed at the bottom surface of the solder resist layer are electrically interfaced to an electrical trace at the substrate of the substrate package. Other related embodiments are disclosed.

公开(公告)号：US20220095484A1

公开(公告)日：2022-03-24

申请号：US17541663

申请日：2021-12-03

Applicant: Intel Corporation

Inventor： Twan Sing Loo ,  Jeff Ku ,  Min Suet Lim ,  Khai Ern Ke See ,  Mark Carbone

IPC: H05K7/20 ,  F28F13/18 ,  G06F1/20

Abstract: Particular embodiments described herein provide for an electronic device that can be configured to include a vapor chamber that includes ionized fluid and an adjustable polarization layer coupled to the vapor chamber. The adjustable polarization layer can be used to direct a flow of the ionized fluid in the vapor chamber towards one or more heat sources. In some examples, the ionized fluid is ionized water and the adjustable polarization layer is polyester (PET) film that includes a plurality of electrode stripes.

公开(公告)号：US11264160B2

公开(公告)日：2022-03-01

申请号：US16402467

申请日：2019-05-03

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Jiun Hann Sir ,  Min Suet Lim ,  Chin Lee Kuan ,  Siew Fong Yap

IPC: H01F27/02 ,  G05F1/56

Abstract: An electronic device comprises an air core inductor including an electronic semiconductor package including a first portion of the air core inductor internal to the electronic semiconductor package; and an electrically conductive layer arranged on a first external surface of the electronic semiconductor package and electrically connected as a second portion of the air core inductor.

公开(公告)号：US20220015272A1

公开(公告)日：2022-01-13

申请号：US17482244

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Yew San Lim ,  Jeff Ku ,  Boon Ping Koh ,  Min Suet Lim ,  Tin Poay Chuah

IPC: H05K9/00 ,  H05K1/02 ,  H05K7/20

Abstract: Particular embodiments described herein provide for an electronic device that can be configured to include a radiation shield that includes a zipper. The radiation shield can include a wall that extends from a support structure of the electronic device, a first portion that is coupled to a cold plate over a radiation source, a second portion that is coupled to the wall, and a zipper that can zip the first portion to the second portion together and can unzip to separate the first portion from the second portion

公开(公告)号：US20210385942A1

公开(公告)日：2021-12-09

申请号：US16988759

申请日：2020-08-10

Applicant: Intel Corporation

Inventor： Tai Loong Wong ,  Fern Nee Tan ,  Tin Poay Chuah ,  Min Suet Lim ,  Siang Yeong Tan

IPC: H05K1/02 ,  H05K1/14

Abstract: The present disclosure generally relates to a scalable computer circuit board having a first power level semiconductor package coupled to at least one base-level voltage regulator module, which is coupled to a plurality of connection receptacles that are configured for connecting with a voltage regulator module positioned on a second level, as a standardized base unit. To scale the base unit, a second power level semiconductor package may be exchanged for the first power level semiconductor package in conjunction with one or more voltage regulator module board being positioned over a corresponding number of base-level voltage regulator modules and coupled to their plurality of connection receptacles.