公开(公告)号：US20170323966A1

公开(公告)日：2017-11-09

申请号：US15656290

申请日：2017-07-21

Applicant: Intel Corporation

Inventor： Sameer S. Pradhan ,  Subhash M. Joshi ,  Jin-Sung Chun

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/66 ,  H01L29/45 ,  H01L29/417 ,  H01L29/16 ,  H01L23/48 ,  H01L21/3205 ,  H01L21/283

CPC classification number: H01L29/785 ,  H01L21/02 ,  H01L21/02532 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/32053 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L23/48 ,  H01L29/16 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure.

公开(公告)号：US09653584B2

公开(公告)日：2017-05-16

申请号：US15037644

申请日：2013-12-23

Applicant: Intel Corporation

Inventor： Glenn A. Glass ,  Anand S. Murthy ,  Daniel B. Aubertine ,  Subhash M. Joshi

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L21/304 ,  H01L21/306 ,  H01L27/105 ,  H01L29/04

CPC classification number: H01L29/785 ,  H01L21/304 ,  H01L21/30604 ,  H01L27/0886 ,  H01L27/105 ,  H01L29/04 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7849

Abstract: Transistor fin elements (e.g., fin or tri gate) may be modified by radio frequency (RF) plasma and/or thermal processing for purpose of dimensional sculpting. The etched, thinned fins may be formed by first forming wider single crystal fins, and after depositing trench oxide material between the wider fins, etching the wider fins using a second etch to form narrower single crystal fins having undamaged top and sidewalls for epitaxially growing active channel material. The second etch may remove a thickness of between a 1 nm and 15 nm of the top surfaces and the sidewalls of the wider fins. It may remove the thickness using (1) chlorine or fluorine based chemistry using low ion energy plasma processing, or (2) low temperature thermal processing that does not damage fins via energetic ion bombardment, oxidation or by leaving behind etch residue that could disrupt the epitaxial growth quality of the second material.

公开(公告)号：US20150155385A1

公开(公告)日：2015-06-04

申请号：US14618414

申请日：2015-02-10

Applicant: INTEL CORPORATION

Inventor： Sameer S. Pradhan ,  Subhash M. Joshi ,  Jin-Sung Chun

IPC: H01L29/78 ,  H01L29/45 ,  H01L21/3205 ,  H01L29/16 ,  H01L21/02 ,  H01L21/283 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/785 ,  H01L21/02 ,  H01L21/02532 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/32053 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L23/48 ,  H01L29/16 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure.

Abstract translation: 本说明书涉及制造具有非平面晶体管的微电子器件的领域。 本发明的实施例涉及在非平面晶体管内形成源极/漏极接触，其中可以使用含钛接触界面来形成源极/漏极接触，其中形成在含钛的 界面和含硅源/排水结构。