公开(公告)号：US20220083419A1

公开(公告)日：2022-03-17

申请号：US17534944

申请日：2021-11-24

Applicant: Intel Corporation

Inventor： Xin Guo ,  Ravi Motwani ,  Donia Sebastian ,  Aaron Lutzker

IPC: G06F11/10 ,  G06F11/07 ,  G06F3/06 ,  G06F7/58

Abstract: Systems, apparatuses and methods may provide for technology that generates a first set of scrambler bits based on a destination page number associated with data, generates a second set of scrambler bits based on a programmable nonlinear function, and combines the first set of scrambler bits and the second set of scrambler bits into a scrambler seed. In one example, the technology also randomizes the data based on the scrambler seed to obtain outgoing randomized data and writes the outgoing randomized data to a non-volatile memory.

公开(公告)号：US20210392083A1

公开(公告)日：2021-12-16

申请号：US17355915

申请日：2021-06-23

Applicant: Intel Corporation

Inventor： Shirish Bahirat ,  Anand Ramalingam ,  Solomon Sagar Albert Jayaraj ,  Fnu Sachin ,  Xin Guo

IPC: H04L12/851

Abstract: Systems, apparatuses and methods provide for a memory controller to manage quality of service enforcement. For example, a memory controller includes logic to determine a plurality of projected bandwidth levels and a plurality of projected quality of service levels on a user-by-user basis. The projected bandwidth levels and the projected quality of service levels are determined for a plurality of device configurations based on one or more storage device parameters. A requested bandwidth level and a requested quality of service level is received from a host in response to the plurality of projected bandwidth levels and the plurality of projected quality of service levels.

公开(公告)号：US10956081B2

公开(公告)日：2021-03-23

申请号：US16388761

申请日：2019-04-18

Applicant: INTEL CORPORATION

Inventor： David J. Pelster ,  David B. Carlton ,  Mark Anthony Golez ,  Xin Guo ,  Aliasgar S. Madraswala ,  Sagar S. Sidhpura ,  Sagar Upadhyay ,  Neelesh Vemula ,  Yogesh B. Wakchaure ,  Ye Zhang

IPC: G06F3/06

Abstract: A data structure is maintained for performing a program operation that is allowed to be suspended to perform reads in a NAND device, where the data structure indicates a plurality of tiers, where each tier of the plurality of tiers has a number of allowed suspends of the program operation while executing in the tier, and where a sum of the number of allowed suspends for all tiers of the plurality of tiers equals a maximum allowed number of suspends of the program operation. In response to performing a resume of the program operation, after performing a read following a suspend of the program operation, a determination is made of a tier of the plurality of tiers for the program operation and a subsequent suspend of the program operation is performed only after a measure of progress of the program operation has been exceeded in the determined tier.

公开(公告)号：US10817180B2

公开(公告)日：2020-10-27

申请号：US16113804

申请日：2018-08-27

Applicant: Intel Corporation

Inventor： Yogesh B. Wakchaure ,  Xin Guo ,  David J. Pelster ,  Eric L. Hoffman

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02 ,  G11C11/56 ,  G11C16/10 ,  G11C16/20 ,  G06F13/00 ,  G06F13/28 ,  G11C16/04

Abstract: An example apparatus includes a non-volatile memory including a first memory having a first write rate and a second memory having a second write rate, the first write rate greater than the second write rate An example controller is to determine, based on a ratio, a first portion of the data to be written to the first memory, and a second portion of the data to be written to the second memory type, the second portion of the data not included in the first portion of the data.

公开(公告)号：US10585791B2

公开(公告)日：2020-03-10

申请号：US15925907

申请日：2018-03-20

Applicant: Intel Corporation

Inventor： Yu Du ,  Ryan Norton ,  David J. Pelster ,  Xin Guo

IPC: G06F12/02 ,  G06F7/58 ,  G06F12/06

Abstract: An embodiment of a semiconductor apparatus may include technology to determine a differentiator associated with an access request for two or more memory devices, and set a target order for the two or more memory devices based on the differentiator. Other embodiments are disclosed and claimed.

公开(公告)号：US10579269B2

公开(公告)日：2020-03-03

申请号：US16105363

申请日：2018-08-20

Applicant: INTEL CORPORATION

Inventor： Aliasgar S. Madraswala ,  Yogesh B. Wakchaure ,  David B. Carlton ,  Xin Guo ,  Ryan J. Norton

IPC: G06F12/00 ,  G06F3/06

Abstract: A first type of command is suspended, by a controller of a non-volatile memory device, in response to determining that a second type of command is waiting for execution. The first type of command is split into a plurality of chunks based on a computed criteria. A second type of command is executed in between execution of at least two chunks of the first type of command.

公开(公告)号：US10521121B2

公开(公告)日：2019-12-31

申请号：US15394653

申请日：2016-12-29

Applicant: INTEL CORPORATION

Inventor： David B. Carlton ,  Xin Guo ,  Yu Du

IPC: G06F12/02 ,  G06F3/06

Abstract: Provided are an apparatus, system and method for apparatus, system and method for throttling an acceptance rate for adding host Input/Output (I/O) commands to a buffer in a non-volatile memory storage device. Information is maintained on an input rate at which I/O commands are being added to the buffer and information is maintained on an output rate at which I/O commands are processed from the buffer to apply to execute against the non-volatile memory. A determination is made of a current level of available space in the buffer and an acceptance rate at which I/O commands are added to the buffer from the host system to process based on the input rate, the output rate, the current level of available space, and an available space threshold for the buffer to maintain the buffer at the available space threshold. I/O commands are added to the buffer to process based on the acceptance rate. The I/O commands are accessed from the buffer to process to execute against the non-volatile memory.

公开(公告)号：US10453540B2

公开(公告)日：2019-10-22

申请号：US15959538

申请日：2018-04-23

Applicant: Intel Corporation

Inventor： Xin Guo ,  Yu Du ,  Curtis Gittens ,  David J. Pelster ,  Donia Sebastian

IPC: G11C16/30 ,  G11C16/26 ,  G11C16/32 ,  G06F3/06 ,  G06F13/18

Abstract: A reduction in Quality of Service (QoS) latency for host read commands in a power limited operation mode in a storage device is provided. A priority level is assigned to a host command using weighted round robin arbitration. Power resources are allocated based on the priority levels assigned to host commands to minimize host read command latency in the power limited operation mode.

公开(公告)号：US10276252B2

公开(公告)日：2019-04-30

申请号：US15838202

申请日：2017-12-11

Applicant: Intel Corporation

Inventor： Aliasgar S. Madraswala ,  Xin Guo ,  Ali Khakifirooz ,  Pranav Kalavade ,  Sagar Upadhyay

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/22 ,  G11C16/10 ,  G11C11/56

Abstract: Embodiments of the present disclosure may relate to a memory controller that may include a memory interface and a logic circuitry component coupled with the memory interface. In some embodiments, the logic circuitry component is to program one or more NAND cells of a multi-level NAND memory array via the memory interface with a first set of data in a first pass, determine a first temperature of the multi-level NAND memory array in association with the first pass, determine a second temperature of the multi-level NAND memory array, determine a temperature difference between the second temperature and the first temperature, and perform one or more operations based at least in part on a result of the determination of the temperature difference. Other embodiments may be described and/or claimed.

公开(公告)号：US10268407B1

公开(公告)日：2019-04-23

申请号：US15721351

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Aliasgar S. Madraswala ,  Xin Guo ,  Naveen Vittal Prabhu ,  Yu Du ,  Purval Shyam Sule

IPC: G11C16/26 ,  G06F3/06

Abstract: In one embodiment, an apparatus comprises a memory array and a controller. The controller is to receive a first read command specifying a read voltage offset profile identifier; identify a read voltage offset profile associated with the read voltage offset profile identifier, the read voltage offset profile comprising at least one read voltage offset; and perform a first read operation specified by the first read command using at least one read voltage adjusted according to the at least one read voltage offset of the read voltage offset profile.