公开(公告)号：US09372231B2

公开(公告)日：2016-06-21

申请号：US14985681

申请日：2015-12-31

Applicant: International Business Machines Corporation

Inventor： Dzmitry S. Maliuk ,  Franco Stellari ,  Alan J. Weger ,  Peilin Song

IPC: G01R31/28 ,  G01R31/3177 ,  G01R31/317 ,  G01R31/3185

CPC classification number: G01R31/3177 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/318516 ,  G01R31/318519 ,  G01R31/318541 ,  G01R31/318572

Abstract: A scan chain latch circuit, a method of operating a latch circuit in a scan chain, and a computer-readable medium having stored thereon a data structure defining a scan chain latch circuit for instantiation on a semiconductor die are disclosed. In an embodiment, the scan chain latch circuit comprises a first latch for holding one data value, a second latch for holding another data value, and a multiplexor. The one data value is applied to a first data input of the multiplexor and the another data value is applied to a second data input of the multiplexor. An alternating clock signal is applied to a select input of the multiplexor to control the output of the multiplexor, wherein the output of the multiplexor toggles between the two data values held in the two latches at a defined frequency.

公开(公告)号：US20160116534A1

公开(公告)日：2016-04-28

申请号：US14985681

申请日：2015-12-31

Applicant: International Business Machines Corporation

Inventor： Dzmitry S. Maliuk ,  Franco Stellari ,  Alan J. Weger ,  Peilin Song

IPC: G01R31/3177 ,  G01R31/317

CPC classification number: G01R31/3177 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/318516 ,  G01R31/318519 ,  G01R31/318541 ,  G01R31/318572

Abstract: A scan chain latch circuit, a method of operating a latch circuit in a scan chain, and a computer-readable medium having stored thereon a data structure defining a scan chain latch circuit for instantiation on a semiconductor die are disclosed. In an embodiment, the scan chain latch circuit comprises a first latch for holding one data value, a second latch for holding another data value, and a multiplexor. The one data value is applied to a first data input of the multiplexor and the another data value is applied to a second data input of the multiplexor. An alternating clock signal is applied to a select input of the multiplexor to control the output of the multiplexor, wherein the output of the multiplexor toggles between the two data values held in the two latches at a defined frequency.

公开(公告)号：US11748524B2

公开(公告)日：2023-09-05

申请号：US16933509

申请日：2020-07-20

Applicant: International Business Machines Corporation

Inventor： Jean-Olivier Plouchart ,  Dirk Pfeiffer ,  Arvind Kumar ,  Takashi Ando ,  Peilin Song

IPC: G06F21/86 ,  G06F21/14 ,  G06F21/79 ,  G06F21/73

CPC classification number: G06F21/86 ,  G06F21/14 ,  G06F21/79

Abstract: An obfuscation circuit relies on a tamper-resistant nonvolatile memory which encodes a trusted Boolean function. The Boolean function is used to enable several operations relating to circuit obfuscation, including obfuscation of logic circuitry, obfuscation of operand data, and release of IP blocks. The tamper-resistant nonvolatile memory is part of a trusted integrated circuit structure, i.e., one fabricated by a trusted foundry, separate from another integrated circuit structure which contains the various operational logic circuits of the design and is fabricated by an untrusted foundry. The Boolean function is encoded based on a look-up table implemented as a cascaded multiplexer circuit. Multiple obfuscation functions can be so encoded. The obfuscation functions may be reprogrammed using a protocol that relies on symmetric keys, one of which is stored in the tamper-resistant nonvolatile memory.

公开(公告)号：US20230170019A1

公开(公告)日：2023-06-01

申请号：US17539295

申请日：2021-12-01

Applicant: International Business Machines Corporation

Inventor： Franco Stellari ,  Ernest Y. Wu ,  Takashi Ando ,  Peilin Song

IPC: G11C13/00 ,  H01L45/00

CPC classification number: G11C13/0064 ,  G11C13/0007 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146

Abstract: System and method to localize a position of an RRAM filament of resistive memory device at very low bias voltages using a scanning laser beam. The approach is non-invasive and allows measurement of a large number of devices for creating statistics relating to the filament formation. A laser microscope system is configured to perform a biasing the RRAM cell with voltage (or current). Concurrent to the applied bias, a laser beam is generated and aimed at different positions of the RRAM cell (e.g., by a raster scanning). Changes in the current (or voltage) flowing through the cell are measured. The method creates a map of the current (or voltage) changes at the different laser positions and detects a spot in the map corresponding to higher (or lower) current (or voltage). The method determines the (x,y) position of the spot compared to the edge/center of the RRAM cell.

公开(公告)号：US20220301134A1

公开(公告)日：2022-09-22

申请号：US17208346

申请日：2021-03-22

Applicant: International Business Machines Corporation

Inventor： Franco Stellari ,  Peilin Song ,  Cyril Cabral, Jr. ,  Steven G. Shevach

IPC: G06T7/00 ,  G06T7/33 ,  G01N21/359 ,  G01N21/88 ,  G06N20/00

Abstract: Circuit board inspection by receiving a near infrared (NIR) image of at least a portion of a circuit board, analyzing the NIR image using a machine learning model, and detecting anomalous circuit board portions according to the analysis.

公开(公告)号：US11105856B2

公开(公告)日：2021-08-31

申请号：US16189295

申请日：2018-11-13

Applicant: International Business Machines Corporation

Inventor： Emily A. Ray ,  Emmanuel Yashchin ,  Peilin Song ,  Kevin G. Stawiasz ,  Barry Linder ,  Alan Weger ,  Keith A. Jenkins ,  Raphael P. Robertazzi ,  Franco Stellari ,  James Stathis

IPC: G06F11/22 ,  G01R31/3193 ,  G01R31/319

Abstract: Methods and systems of detecting chip degradation are described. A processor may execute a test on a device at a first time, where the test includes executable instructions for the device to execute a task under specific conditions relating to a performance attribute. The processor may receive performance data indicating a set of outcomes from the task executed by the device during the test. The processor may determine a first value of a parameter of the performance attribute based on the identified subset. The processor may compare the first value with a second value of the parameter of the performance attribute. The second value is based on an execution of the test on the device at a second time. The processor may determine a degradation status of the device based on the comparison of the first value with the second value.

公开(公告)号：US20190325568A1

公开(公告)日：2019-10-24

申请号：US15955974

申请日：2018-04-18

Applicant: International Business Machines Corporation

Inventor： Franco Stellari ,  Chung-Ching Lin ,  Peilin Song

IPC: G06T5/50 ,  G02B21/24 ,  G06T5/00 ,  G02B7/36

Abstract: Systems, computer-implemented methods, and computer program products to focus a microscope. A system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise an analyzer component that can analyze sub-images of respective sample images to identify one or more sub-images having a maximized variance of a gradient derivative corresponding to the one or more sub-images. The respective sample images can be acquired at one or more focal positions along an optical axis of a microscope. The computer executable components can further comprise a selection component that can select an image, from the respective sample images, that comprises the one or more sub-images identified. The computer executable components can also comprise a focus component that, based on a focal position corresponding to the image selected, can focus the microscope to the focal position.

公开(公告)号：US20190180430A1

公开(公告)日：2019-06-13

申请号：US15834602

申请日：2017-12-07

Applicant: International Business Machines Corporation

Inventor： Chung-Ching Lin ,  Thomas McCarroll Shaw ,  Peilin Song ,  Franco Stellari ,  Thomas Anthony Wassick

IPC: G06T7/00

Abstract: Techniques that facilitate integrated circuit defect detection using pattern images are provided. In one example, a system generates an equalized pattern image of a pattern image associated with a module under test based on an adaptive contrast equalization technique. The system also identifies a first set of features of the equalized pattern image based on a feature point detection technique and aligns the equalized pattern image with a reference pattern image based on the first set of features and a second set of features of the reference pattern image. Furthermore, the system compares a first set of light intensities of the equalized pattern image to a second set of light intensities of the reference pattern image to identify one or more regions of the module under test that satisfy a defined criterion associated with a defect for the module under test.

公开(公告)号：US20180211377A1

公开(公告)日：2018-07-26

申请号：US15414569

申请日：2017-01-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Andrea Bahgat Shehata ,  Peilin Song ,  Franco Stellari ,  Alan J. Weger

IPC: G06T7/00 ,  H01L23/00 ,  H01L21/66 ,  G06T11/20 ,  G06K9/62 ,  G01N21/956 ,  G01N21/95

CPC classification number: G06T7/0004 ,  G01N21/9501 ,  G01N21/95607 ,  G01N2201/13 ,  G06K9/6201 ,  G06K9/6267 ,  G06T11/20 ,  G06T2207/30148 ,  H01L22/30 ,  H01L23/57 ,  H01L23/573

Abstract: A computer-implemented device and method for identifying hardware Trojans and defects based on light emissions from Integrated Circuits (ICs) is provided. A measured emissions map is received based on light emissions captured from a sacrificial test IC. The sacrificial test IC is a partially manufactured IC fabricated to include a set of frontend layers of an IC architecture but not a set of backend layers of the IC architecture. The sacrificial test IC also includes a sacrificial layer for powering devices in the partially manufactured IC without the set of backend layers. An expected emissions map is derived from the sacrificial test IC and the measured emissions map is compared with the expected emissions map to identify deviations from the IC architecture in the frontend layers.

公开(公告)号：US09678152B2

公开(公告)日：2017-06-13

申请号：US15138737

申请日：2016-04-26

Applicant: International Business Machines Corporation

Inventor： Dzmitry S. Maliuk ,  Franco Stellari ,  Alan J. Weger ,  Peilin Song

IPC: G06F11/00 ,  G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/318516 ,  G01R31/318519 ,  G01R31/318541 ,  G01R31/318572

Abstract: A scan chain latch circuit, a method of operating a latch circuit in a scan chain, and a computer-readable medium having stored thereon a data structure defining a scan chain latch circuit for instantiation on a semiconductor die are disclosed. In an embodiment, the scan chain latch circuit comprises a first latch for holding one data value, a second latch for holding another data value, and a multiplexor. The one data value is applied to a first data input of the multiplexor and the another data value is applied to a second data input of the multiplexor. An alternating clock signal is applied to a select input of the multiplexor to control the output of the multiplexor, wherein the output of the multiplexor toggles between the two data values held in the two latches at a defined frequency.