公开(公告)号：US10734281B2

公开(公告)日：2020-08-04

申请号：US15699695

申请日：2017-09-08

Applicant: International Business Machines Corporation

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Shogo Mochizuki ,  Hao Tang

IPC: H01L21/768 ,  H01L27/092 ,  B82Y40/00

Abstract: A self-assembled heteroepitaxial oxide nanocomposite film including alternating layers of a first metal oxide having a first melting point and a second metal oxide having a second melting point that differs from the first melting point is formed in an opening formed in a semiconductor substrate. After forming a metal or metal alloy via structure in the semiconductor substrate, first and second thermal treatments are performed to remove each layer of first or second metal oxide providing a nanoporous membrane.

公开(公告)号：US10686057B2

公开(公告)日：2020-06-16

申请号：US15951510

申请日：2018-04-12

Applicant: International Business Machines Corporation

Inventor： Choonghyun Lee ,  Kangguo Cheng ,  Juntao Li ,  Shogo Mochizuki

IPC: H01L29/66 ,  H01L29/08 ,  H01L21/225 ,  H01L21/306 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/28

Abstract: Methods of fabrication and semiconductor structures includes vertical transport field effect transistors (VTFETs) including a top source/drain extension formed with a sacrificial doped layer. The sacrificial doped layer provides the doping source to form the extension and protects the top of the fin during fabrication so as to prevent thinning, among other advantages.

公开(公告)号：US10679901B2

公开(公告)日：2020-06-09

申请号：US16103433

申请日：2018-08-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Huimei Zhou ,  Shogo Mochizuki ,  Gen Tsutsui ,  Ruqiang Bao

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311

Abstract: Integrated chips and methods of forming the same include etching a first stack of layers in a first region and etching a second stack of layers in a second region. The first stack of layers includes a first semiconductor layer having a first thickness over a first sacrificial layer having a second thickness. Etching the first stack of layers removes the first sacrificial layer from the first stack of layers and creates a first gap. The second stack of layers includes a second semiconductor layer having a third thickness over a second sacrificial layer having a fourth thickness. Etching the second stack of layers removes the second sacrificial layer from the second stack of layers and to create a second gap. A dielectric material fills the first gap and the second gap.

公开(公告)号：US10665714B2

公开(公告)日：2020-05-26

申请号：US16023535

申请日：2018-06-29

Applicant: International Business Machines Corporation

Inventor： Juntao Li ,  Kangguo Cheng ,  ChoongHyun Lee ,  Shogo Mochizuki

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L29/10

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of fins on a semiconductor substrate. In the method, at least two spacer layers are formed around a first fin of the plurality of fins, and a single spacer layer is formed around a second fin of the plurality of fins. The at least two spacer layers include a first spacer layer including a first material and a second spacer layer including a second material different from the first material. The single spacer layer includes the second material. The method also includes selectively removing part of the first spacer layer to expose part of the first fin, and epitaxially growing a source/drain region around the exposed part of the first fin.

公开(公告)号：US20200161453A1

公开(公告)日：2020-05-21

申请号：US16752263

申请日：2020-01-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Juntao Li ,  Choonghyun Lee ,  Shogo Mochizuki

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06

Abstract: A method of forming a fin field effect transistor device is provided. The method includes forming a plurality of vertical fins on a substrate. The method further includes forming a bottom source/drain layer adjacent to the plurality of vertical fins, and growing a doped layer on the bottom source/drain layer and sidewalls of the plurality of vertical fins. The method further includes forming a dummy gate liner on the doped layer and the bottom source/drain layer, and forming a dummy gate fill on the dummy gate liner. The method further includes forming a protective cap layer on the dummy gate fill, and removing a portion of the protective cap layer to expose a top surface of the plurality of vertical fins.

公开(公告)号：US20200035823A1

公开(公告)日：2020-01-30

申请号：US16592389

申请日：2019-10-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Huimei Zhou ,  Su Chen Fan ,  Shogo Mochizuki ,  Peng Xu ,  Nicolas J. Loubet

IPC: H01L29/78 ,  H01L27/06 ,  H01L29/08 ,  H01L29/66 ,  H01L27/092

Abstract: A method of forming stacked fin field effect devices is provided. The method includes forming a layer stack on a substrate, wherein the layer stack includes a first semiconductor layer on a surface of the substrate, a second semiconductor layer on the first semiconductor layer, a third semiconductor layer on the second semiconductor layer, a separation layer on the third semiconductor layer, a fourth semiconductor layer on the separation layer, a fifth semiconductor layer on the fourth semiconductor layer, and a sixth semiconductor layer on the fifth semiconductor layer. The method further includes forming a plurality of channels through the layer stack to the surface of the substrate, and removing portions of the second semiconductor layer and fifth semiconductor layer to form lateral grooves.

公开(公告)号：US10535773B2

公开(公告)日：2020-01-14

申请号：US16234985

申请日：2018-12-28

Applicant: International Business Machines Corporation

Inventor： Dechao Guo ,  Hemanth Jagannathan ,  Shogo Mochizuki ,  Gen Tsutsui ,  Chun-Chen Yeh

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/165 ,  H01L29/66 ,  H01L21/02

Abstract: After forming a gate structure over a semiconductor fin that extends upwards from a semiconductor substrate portion, a sigma cavity is formed within the semiconductor fin on each side of the gate structure. A semiconductor buffer region composed of an un-doped stress-generating semiconductor material is epitaxially growing from faceted surfaces of the sigma cavity. Finally, a doped semiconductor region composed of a doped stress-generating semiconductor material is formed on the semiconductor buffer region to completely fill the sigma cavity. The doped semiconductor region is formed to have substantially vertical sidewalls for formation of a uniform source/drain junction profile.

公开(公告)号：US10529851B1

公开(公告)日：2020-01-07

申请号：US16033994

申请日：2018-07-12

Applicant: International Business Machines Corporation

Inventor： Shogo Mochizuki ,  Kangguo Cheng ,  Juntao Li ,  Choonghyun Lee

IPC: H01L29/78 ,  H01L21/225 ,  H01L21/324 ,  H01L29/66 ,  H01L29/49 ,  H01L29/08 ,  H01L21/768 ,  H01L29/167 ,  H01L21/02 ,  H01L21/28 ,  H01L29/161

Abstract: Techniques for forming bottom source and drain extensions in VTFET devices are provided. In one aspect, a method of forming a VTFET device includes: patterning fins in a wafer; forming a liner at a base of the fins having a higher diffusivity for dopants than the fins; forming sidewall spacers alongside an upper portion of the fins; forming bottom source/drains on the liner at the base of the fins including the dopants; annealing the wafer to diffuse the dopants from the bottom source/drains, through the liner, into the base of the fins to form bottom extensions; removing the sidewall spacers; forming bottom spacers on the bottom source/drains; forming gate stacks alongside the fins above the bottom spacers; forming top spacers above the gate stacks; and forming top source/drains above the top spacers at tops of the fins. A VTFET device is also provided.

公开(公告)号：US10510617B2

公开(公告)日：2019-12-17

申请号：US15918077

申请日：2018-03-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Oleg Gluschenkov ,  Zuoguang Liu ,  Shogo Mochizuki ,  Hiroaki Niimi ,  Tenko Yamashita

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/51 ,  H01L29/24 ,  H01L29/161

Abstract: Embodiments are directed to a complementary metal oxide semiconductor having source and drain contacts formed using trench. An n-type field effect transistor (NFET) includes a p-type semiconductor fin vertically extending from an n-type bottom source or drain region disposed on the substrate. A p-type FET (PFET) includes an n-type semiconductor fin vertically extending from a p-type bottom source or drain region disposed on the substrate. A first gate of the NFET is formed around a channel region of the p-type semiconductor fin and a second gate of the PFET is formed around a channel region of the n-type semiconductor fin. The first gate and the second gate include a dipole layer. The NFET and PFET each has a threshold voltage of about 150 mV to about 250 mV and a difference between the threshold voltages of the NFET and PFET is less than about 50 mV.

公开(公告)号：US20190355845A1

公开(公告)日：2019-11-21

申请号：US15979589

申请日：2018-05-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Huimei Zhou ,  Su Chen Fan ,  Shogo Mochizuki ,  Peng Xu ,  Nicolas J. Loubet

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L27/06 ,  H01L27/092

Abstract: A method of forming stacked fin field effect devices is provided. The method includes forming a layer stack on a substrate, wherein the layer stack includes a first semiconductor layer on a surface of the substrate, a second semiconductor layer on the first semiconductor layer, a third semiconductor layer on the second semiconductor layer, a separation layer on the third semiconductor layer, a fourth semiconductor layer on the separation layer, a fifth semiconductor layer on the fourth semiconductor layer, and a sixth semiconductor layer on the fifth semiconductor layer. The method further includes forming a plurality of channels through the layer stack to the surface of the substrate, and removing portions of the second semiconductor layer and fifth semiconductor layer to form lateral grooves.