公开(公告)号：US07939852B2

公开(公告)日：2011-05-10

申请号：US12176835

申请日：2008-07-21

Applicant: Rohit Pal ,  Frank Bin Yang ,  Michael J. Hargrove

Inventor： Rohit Pal ,  Frank Bin Yang ,  Michael J. Hargrove

IPC: H01L31/0328

CPC classification number: H01L29/66636 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7848

Abstract: Semiconductor transistor devices and related fabrication methods are provided. An exemplary transistor device includes a layer of semiconductor material having a channel region defined therein and a gate structure overlying the channel region. Recesses are formed in the layer of semiconductor material adjacent to the channel region, such that the recesses extend asymmetrically toward the channel region. The transistor device also includes stress-inducing semiconductor material formed in the recesses. The asymmetric profile of the stress-inducing semiconductor material enhances carrier mobility in a manner that does not exacerbate the short channel effect.

Abstract translation: 提供半导体晶体管器件及相关制造方法。 示例性晶体管器件包括其中限定有沟道区的半导体材料层和覆盖沟道区的栅极结构。 凹槽在与沟道区相邻的半导体材料层中形成，使得凹槽朝向沟道区不对称地延伸。 晶体管器件还包括形成在凹槽中的应力诱导半导体材料。 应力诱导半导体材料的不对称轮廓以不会加剧短通道效应的方式提高载流子迁移率。

公开(公告)号：US20110062519A1

公开(公告)日：2011-03-17

申请号：US12561638

申请日：2009-09-17

Applicant: Rohit Pal ,  Stephan Waidmann

Inventor： Rohit Pal ,  Stephan Waidmann

IPC: H01L29/78 ,  H01L21/762

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/78

Abstract: Semiconductor devices with high-K/metal gates are formed with spacers that are substantially resistant to subsequent etching to remove an overlying spacer, thereby avoiding replacement and increasing manufacturing throughput. Embodiments include forming a high-K/metal gate, having an upper surface and side surfaces, over a substrate, e.g., a SOI substrate, and sequentially forming, on the side surfaces of the high-K/metal gate, a first spacer of a non-oxide material, a second spacer, of a material different from that of the first spacer, and a third spacer, of a material different from that of the second spacer. After formation of source and drain regions, e.g., epitaxially grown silicon-germanium, the third spacer is etched with an etchant, such as hot phosphoric acid, to which the second spacer is substantially resistant, thereby avoiding replacement.

Abstract translation: 具有高K /金属栅极的半导体器件由间隔物形成，其具有基本上抵抗后续蚀刻以去除上覆间隔物，从而避免替换并增加制造生产量。 实施例包括在衬底（例如SOI衬底）上形成具有上表面和侧表面的高K /金属栅极，并且在高K /金属栅极的侧表面上依次形成第一间隔物 不同于第一间隔物的材料的非氧化物材料，第二间隔物和与第二间隔物不同的材料的第三间隔物。 在形成源极和漏极区域，例如外延生长的硅 - 锗之后，用蚀刻剂（例如热磷酸）蚀刻第三间隔物，第二间隔物基本上抵抗其上，从而避免更换。

公开(公告)号：US07838308B2

公开(公告)日：2010-11-23

申请号：US12119196

申请日：2008-05-12

Applicant: Rohit Pal ,  David E. Brown ,  Alok Vaid ,  Kevin Lensing

Inventor： Rohit Pal ,  David E. Brown ,  Alok Vaid ,  Kevin Lensing

IPC: H01L21/00

CPC classification number: H01L29/7848 ,  H01L22/12 ,  H01L22/20 ,  H01L29/66636 ,  H01L29/78

Abstract: A method that includes forming a gate of a semiconductor device on a substrate and forming a recess for an embedded silicon-straining material in source and drain regions for the gate. In this method, a proximity value, which is defined as a distance between the gate and a closest edge of the recess, is controlled by controlling formation of an oxide layer provided beneath the gate. The method can also include feedforward control of process steps in the formation of the recess based upon values measured during the formation of the recess. The method can also apply feedback control to adjust a subsequent recess formation process performed on a subsequent semiconductor device based on the comparison between a measured proximity value and a target proximity value to decrease a difference between a proximity value of the subsequent semiconductor device and the target proximity value.

Abstract translation: 一种方法，包括在衬底上形成半导体器件的栅极，并在栅极的源极和漏极区域中形成嵌入的硅应变材料的凹部。 在该方法中，通过控制形成在栅极下方的氧化物层来控制被定义为栅极和凹部的最近边缘之间的距离的接近值。 该方法还可以包括基于在形成凹部期间测量的值来形成凹部中的工艺步骤的前馈控制。 该方法还可以基于测量的接近度值和目标接近值之间的比较来应用反馈控制来调整对随后的半导体器件执行的随后的凹陷形成处理，以减小随后的半导体器件的接近值与目标之间的差异 接近值。

公开(公告)号：US20100244156A1

公开(公告)日：2010-09-30

申请号：US12815129

申请日：2010-06-14

Applicant: Rohit Pal ,  Man Fai Ng ,  David Brown

Inventor： Rohit Pal ,  Man Fai Ng ,  David Brown

IPC: H01L29/78

CPC classification number: H01L29/6656 ,  H01L21/28114 ,  H01L21/28247

Abstract: Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. In an embodiment, a method for fabricating a semiconductor device comprises forming a gate stack comprising a first gate stack-forming layer overlying a semiconductor substrate and forming first sidewall spacers about sidewalls of the gate stack. After the step of forming the first sidewall spacers, a portion of the first gate stack-forming layer is exposed. The exposed portion is anisotropically etched using the gate stack and the first sidewall spacers as an etch mask. Second sidewall spacers are formed adjacent the first sidewall spacers after the step of anisotropically etching.

Abstract translation: 提供了在由这些方法制造的半导体器件和半导体器件的制造期间保护栅极堆叠的方法。 在一个实施例中，一种用于制造半导体器件的方法包括：形成包括覆盖在半导体衬底上的第一栅极叠层形成层并且围绕栅堆叠的侧壁形成第一侧壁隔离物的栅叠层。 在形成第一侧壁间隔物的步骤之后，暴露第一栅叠层形成层的一部分。 使用栅极堆叠和第一侧壁间隔物作为蚀刻掩模来各向异性蚀刻暴露部分。 在各向异性蚀刻的步骤之后，第二侧壁间隔物邻近第一侧壁间隔件形成。

公开(公告)号：US07682845B2

公开(公告)日：2010-03-23

申请号：US11964935

申请日：2007-12-27

Applicant: Rohit Pal ,  Alok Vaid ,  Kevin Lensing

Inventor： Rohit Pal ,  Alok Vaid ,  Kevin Lensing

IPC: G01R31/26

CPC classification number: H01L22/12 ,  C30B25/16 ,  C30B29/06 ,  H01L21/02532 ,  H01L22/20

Abstract: Methods are provided for calibrating a process for growing an epitaxial silicon-comprising film and for growing an epitaxial silicon-comprising film. One method comprises epitaxially growing a first silicon-comprising film on a first silicon substrate that has an adjacent non-crystalline-silicon structure that extends from said first silicon substrate. The step of epitaxially growing uses hydrochloric acid provided at a first hydrochloric acid flow rate for a first time period. A morphology of the first film relevant to the adjacent non-crystalline-silicon structure is analyzed and a thickness of the first film is measured. The first flow rate is adjusted to a second flow rate based on the morphology of the first film. The first time period is adjusted to a second time period based on the second flow rate and the thickness. A second silicon-comprising film on a second silicon substrate is epitaxially grown for the second time period using the second flow rate.

Abstract translation: 提供了用于校准用于生长外延含硅膜并用于生长外延含硅膜的工艺的方法。 一种方法包括在具有从所述第一硅衬底延伸的相邻非晶硅结构的第一硅衬底上外延生长第一含硅膜。 外延生长的步骤使用以第一次盐酸流速提供的盐酸第一次。 分析与相邻的非晶硅结构相关的第一膜的形态，并测量第一膜的厚度。 基于第一膜的形态将第一流量调节到第二流量。 基于第二流量和厚度将第一时间段调整到第二时间段。 使用第二流量，在第二时间段外延生长第二硅衬底上的第二含硅膜。

公开(公告)号：US08674458B2

公开(公告)日：2014-03-18

申请号：US13483630

申请日：2012-05-30

Applicant: Stephan-Detlef Kronholz ,  Rohit Pal ,  Gunda Beernink

Inventor： Stephan-Detlef Kronholz ,  Rohit Pal ,  Gunda Beernink

IPC: H01L21/02

CPC classification number: H01L29/7848 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834

Abstract: When forming sophisticated semiconductor devices including transistors with sophisticated high-k metal gate electrode structures and a strain-inducing semiconductor alloy, transistor uniformity and performance may be enhanced by providing superior growth conditions during the selective epitaxial growth process. To this end, a semiconductor material may be preserved at the isolation regions in order to avoid the formation of pronounced shoulders. Furthermore, in some illustrative embodiments, additional mechanisms are implemented in order to avoid undue material loss, for instance upon removing a dielectric cap material and the like.

Abstract translation: 当形成具有复杂的高k金属栅电极结构的晶体管和应变诱导半导体合金的复杂半导体器件时，可以通过在选择性外延生长工艺期间提供优异的生长条件来增强晶体管的均匀性和性能。 为此，可以在隔离区域保留半导体材料，以避免突出的肩部的形成。 此外，在一些说明性实施例中，为了避免不适当的材料损失，例如在去除电介质盖材料等时，实施附加机构。

公开(公告)号：US08598009B2

公开(公告)日：2013-12-03

申请号：US13456633

申请日：2012-04-26

Applicant: Brian J. Greene ,  William K. Henson ,  Judson R. Holt ,  Michael D. Steigerwalt ,  Kuldeep Amarnath ,  Rohit Pal ,  Johan W. Weijtmans

Inventor： Brian J. Greene ,  William K. Henson ,  Judson R. Holt ,  Michael D. Steigerwalt ,  Kuldeep Amarnath ,  Rohit Pal ,  Johan W. Weijtmans

IPC: H01L21/8222

CPC classification number: H01L29/66636 ,  H01L21/3247 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7848

Abstract: A low energy surface is formed by a high temperature anneal of the surfaces of trenches on each side of a gate stack. The material of the semiconductor layer reflows during the high temperature anneal such that the low energy surface is a crystallographic surface that is at a non-orthogonal angle with the surface normal of the semiconductor layer. A lattice mismatched semiconductor material is selectively grown on the semiconductor layer to fill the trenches, thereby forming embedded lattice mismatched semiconductor material portions in source and drain regions of a transistor. The embedded lattice mismatched semiconductor material portions can be in-situ doped without increasing punch-through. Alternately, a combination of intrinsic selective epitaxy and ion implantation can be employed to form deep source and drain regions.

Abstract translation: 低能量表面通过栅极堆叠的每一侧的沟槽表面的高温退火形成。 半导体层的材料在高温退火期间回流，使得低能表面是与半导体层的表面法线成非正交角的结晶表面。 在半导体层上选择性地生长晶格失配的半导体材料以填充沟槽，从而在晶体管的源极和漏极区域中形成嵌入的晶格失配的半导体材料部分。 嵌入的晶格不匹配的半导体材料部分可以原位掺杂而不增加穿通。 或者，可以采用固有选择性外延和离子注入的组合来形成深的源极和漏极区域。

公开(公告)号：US20130040430A1

公开(公告)日：2013-02-14

申请号：US13552722

申请日：2012-07-19

Applicant: Rohit Pal ,  Stephan-Detlef Kronholz

Inventor： Rohit Pal ,  Stephan-Detlef Kronholz

IPC: H01L21/8234

CPC classification number: H01L29/1054 ,  H01L21/823807 ,  H01L21/823857 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66651 ,  H01L29/7833 ,  H01L29/7848 ,  Y02P80/30

Abstract: The present disclosure provides manufacturing techniques in which sophisticated high-k metal gate electrode structures may be formed in an early manufacturing stage on the basis of a selectively applied threshold voltage adjusting semiconductor alloy. In order to reduce the surface topography upon patterning the deposition mask while still allowing the usage of well-established epitaxial growth recipes developed for silicon dioxide-based hard mask materials, a silicon nitride base material may be used in combination with a surface treatment. In this manner, the surface of the silicon nitride material may exhibit a silicon dioxide-like behavior, while the patterning of the hard mask may be accomplished on the basis of highly selective etch techniques.

Abstract translation: 本公开提供了其中可以在选择性施加的阈值电压调节半导体合金的基础上在早期制造阶段中形成复杂的高k金属栅电极结构的制造技术。 为了在图案化沉积掩模的同时减少表面形貌，同时仍允许使用为基于二氧化硅的硬掩模材料开发的良好的外延生长配方，可以将氮化硅基材与表面处理组合使用。 以这种方式，氮化硅材料的表面可以表现出二氧化硅的行为，而硬掩模的图案化可以基于高选择性蚀刻技术来实现。

公开(公告)号：US08294211B2

公开(公告)日：2012-10-23

申请号：US12687610

申请日：2010-01-14

Applicant: Bin Yang ,  Rohit Pal ,  Michael Hargrove

Inventor： Bin Yang ,  Rohit Pal ,  Michael Hargrove

IPC: H01L29/786

CPC classification number: H01L27/12 ,  H01L21/84 ,  H01L21/845 ,  H01L23/485 ,  H01L27/1211

Abstract: A method of fabricating a semiconductor device with back side conductive plugs is provided here. The method begins by forming a gate structure overlying a semiconductor-on-insulator (SOI) substrate. The SOI substrate has a support layer, an insulating layer overlying the support layer, an active semiconductor region overlying the insulating layer, and an isolation region outboard of the active semiconductor region. A first section of the gate structure is formed overlying the isolation region and a second section of the gate structure is formed overlying the active semiconductor region. The method continues by forming source/drain regions in the active semiconductor region, and thereafter removing the support layer from the SOI substrate. Next, the method forms conductive plugs for the gate structure and the source/drain regions, where each of the conductive plugs passes through the insulating layer.

Abstract translation: 此处提供制造具有背面导电插头的半导体器件的方法。 该方法通过形成覆盖绝缘体上半导体（SOI）衬底的栅极结构开始。 SOI衬底具有支撑层，覆盖在支撑层上的绝缘层，覆盖绝缘层的有源半导体区域和有源半导体区域外侧的隔离区域。 栅极结构的第一部分形成在隔离区域的上方，栅极结构的第二部分形成在有源半导体区域的上方。 该方法通过在有源半导体区域中形成源极/漏极区域继续，然后从SOI衬底去除支撑层。 接下来，该方法形成用于栅极结构和源极/漏极区域的导电插塞，其中每个导电插塞穿过绝缘层。

公开(公告)号：US20120235245A1

公开(公告)日：2012-09-20

申请号：US13422148

申请日：2012-03-16

Applicant: Rohit Pal ,  Stephan-Detlef Kronholz

Inventor： Rohit Pal ,  Stephan-Detlef Kronholz

IPC: H01L27/088 ,  H01L21/762 ,  H01L21/336

CPC classification number: H01L21/823481 ,  H01L21/76232 ,  H01L21/823878

Abstract: When forming sophisticated semiconductor devices on the basis of high-k metal gate electrode structures, which are to be provided in an early manufacturing stage, the encapsulation of the sensitive gate materials may be improved by reducing the depth of or eliminating recessed areas that are obtained after forming sophisticated trench isolation regions. To this end, after completing the STI module, an additional fill material may be provided so as to obtain the desired surface topography and also preserve superior material characteristics of the trench isolation regions.

Abstract translation: 当在早期制造阶段提供的高k金属栅极电极结构的基础上形成复杂的半导体器件时，可以通过减少获得的凹陷区域的深度或消除凹陷区域来改善敏感栅极材料的封装 形成复杂的沟槽隔离区。 为此，在完成STI模块之后，可以提供另外的填充材料以获得所需的表面形貌并且还保持沟槽隔离区域的优良的材料特性。