公开(公告)号：US20210143211A1

公开(公告)日：2021-05-13

申请号：US17092130

申请日：2020-11-06

Applicant: IMEC vzw

Inventor： Gaspard Hiblot ,  Shamin Houshmand Sharifi ,  Geert Van der Plas

IPC: H01L27/22 ,  G11C11/16 ,  H01L43/02 ,  H01L43/12 ,  G11C5/06

Abstract: The disclosed technology relates to the field of memory devices including memory arrays, and more particularly, to magnetic memory devices. In one aspect, the disclosed technology provides a method of fabricating a memory device, and the memory device. The method comprises: processing a plurality of selector devices in a semiconductor layer of a first substrate, processing an interconnect layer on a front-side of the semiconductor layer, the interconnect layer comprising an interconnect structure electrically connected to the plurality of selector devices, processing a plurality of memory elements in an oxide layer of the first substrate arranged on a back-side of the semiconductor layer, each memory element being electrically connected to one of the selector devices, and processing one or more vias through the semiconductor layer to electrically connect the memory elements to the interconnect structure.

公开(公告)号：US10998413B2

公开(公告)日：2021-05-04

申请号：US16711258

申请日：2019-12-11

Applicant: IMEC vzw

Inventor： Gaspard Hiblot ,  Sylvain Baudot ,  Geert Van der Plas

IPC: H01L21/8234 ,  H01L29/45 ,  H01L21/762 ,  H01L27/088 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/311

Abstract: The disclosed technology relates generally to integrated circuit structures, and more particularly to a semiconductor fin structure having silicided portions. In an aspect, a semiconductor device including a fin structure and a substrate is disclosed. The fin structure includes a first source/drain region, a second source/drain region, and a channel region. The channel region is arranged between the first source/drain region and the second source/drain region to separate the first source/drain region and the second source/drain region in a length direction of the fin structure. The first source/drain region includes a bottom portion and a top portion, wherein the bottom portion of the first source/drain region is fully silicided and the top portion of the first source/drain region is partly silicided.

公开(公告)号：US10607901B2

公开(公告)日：2020-03-31

申请号：US16121369

申请日：2018-09-04

Applicant: IMEC VZW

Inventor： Gaspard Hiblot ,  Geert Van der Plas ,  Stefaan Van Huylenbroeck

IPC: H01L21/66 ,  G01L1/18 ,  G01L1/22 ,  G01L1/16 ,  G01L5/161 ,  H01L21/265

Abstract: An example embodiment may include a sensor for monitoring and/or measuring stress in a semiconductor component. The component may include a substrate formed of a semiconductor material. The substrate may include a planar main surface. The sensor may include at least one slanted surface of the substrate material, the slanted surface being defined by an oblique inclination angle with respect to the main surface of the substrate. The sensor may also include at least one straight resistive path extending on at least part of the slanted surface and a plurality of contacts and terminals for accessing the at least one resistive path. The contacts and terminals may allow for the measurement of an electrical resistance of the resistive path and an assessment of a shear stress in a plane that is not parallel to the main surface of the substrate.

公开(公告)号：US20190181133A1

公开(公告)日：2019-06-13

申请号：US16215492

申请日：2018-12-10

Applicant: IMEC vzw

Inventor： Gaspard Hiblot ,  Geert Van der Plas ,  Stefaan Van Huylenbroeck

IPC: H01L27/02 ,  H01L23/60 ,  H01L23/48 ,  H01L21/3065 ,  H01L21/768

CPC classification number: H01L27/0259 ,  H01L21/3065 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/60 ,  H01L27/0292

Abstract: The disclosed technology relates to a semiconductor integrated circuit that comprises a semiconductor device which has a port to be protected from Plasma-Induced Damage due to electric charge that may accumulate at the port during a plasma-processing step, and a protection circuit that is provided to the integrated circuit. In one aspect, the protection circuit comprises a discharge path, a control terminal, and a plasma pick-up antenna connected to the control terminal. The protection circuit further comprises a bipolar transistor which has a base connected to the control terminal. Such protection circuit is much more efficient in allowing charge transfer from the device port to a reference voltage terminal.