公开(公告)号：US20230208783A1

公开(公告)日：2023-06-29

申请号：US18177417

申请日：2023-03-02

Applicant: Intel Corporation

Inventor： Kevin Clark ,  Scott J. Weber ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu

IPC: H04L49/109 ,  H01L25/065 ,  H04L49/15

CPC classification number: H04L49/109 ,  H01L25/0652 ,  H04L49/15 ,  H01L2225/06517 ,  H01L23/5386

Abstract: This disclosure relates to integrated circuit devices that may include a network processor in a data processing die and an on-package memory in a base die. The data processing die may implement one or more network functionalities that may exchange data with low-latency memory, high capacity in the base die. The data processing die may be programmable fabric, which may be dynamically reconfigured during operation.

公开(公告)号：US11632112B2

公开(公告)日：2023-04-18

申请号：US15855419

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Ravi Prakash Gutala ,  Aravind Raghavendra Dasu ,  Sean R. Atsatt ,  Scott J. Weber

IPC: G06F7/38 ,  H03K19/173 ,  H03K19/0175 ,  G06F3/06 ,  G11C11/417 ,  H01L25/18 ,  H01L27/02 ,  H01L23/48 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00 ,  H01L23/367 ,  G11C7/10 ,  H03K19/17796 ,  G11C5/04 ,  G06F30/34

Abstract: An integrated circuit device having separate dies for programmable logic fabric and circuitry to operate the programmable logic fabric are provided. A first integrated circuit die may include field programmable gate array fabric. A second integrated circuit die may be coupled to the first integrated circuit die. The second integrated circuit die may include fabric support circuitry that operates the field programmable gate array fabric of the first integrated circuit die.

公开(公告)号：US11625245B2

公开(公告)日：2023-04-11

申请号：US16146586

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Eriko Nurvitadhi ,  Scott J. Weber ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu

IPC: G06F9/30 ,  G05B19/05 ,  G06N3/02 ,  G06F15/78 ,  G06F30/34 ,  G06F30/39

Abstract: An integrated circuit device may include programmable logic circuitry on a first integrated circuit die and memory that includes compute-in-memory circuitry on a second die. The programmable logic circuitry may be programmed with a circuit design that operates on a first set of data. The compute-in-memory circuitry of the memory may perform an arithmetic operation using the first set of data from the programmable logic circuitry and a second set of data stored in the memory.

公开(公告)号：US20220294454A1

公开(公告)日：2022-09-15

申请号：US17710628

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Sean R. Atsatt ,  Scott J. Weber ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu

IPC: H03K19/17758 ,  H03K19/1776 ,  H03K19/17796 ,  H03K19/17772 ,  H03K19/17768

Abstract: An integrated circuit device may include programmable logic fabric disposed on a first integrated circuit die, such that the programmable logic fabric may include a first region of programmable logic fabric and a second region of programmable logic fabric. The first region of programmable logic fabric is configured to be programmed with a circuit design that operates on a first set of data. The integrated circuit may also include network on chip (NOC) circuitry disposed on a second integrated circuit die, such that the NOC circuitry is configured to communicate data between the first integrated circuit die and the second integrated circuit die.

公开(公告)号：US11101804B2

公开(公告)日：2021-08-24

申请号：US16711330

申请日：2019-12-11

Applicant: Intel Corporation

Inventor： Scott Jeremy Weber ,  Aravind Raghavendra Dasu ,  Mahesh A. Iyer ,  Patrick Koeberl

IPC: H03K19/17756 ,  H01L25/065 ,  H01L25/00

Abstract: An integrated circuit device may include a programmable fabric die having programmable logic fabric and configuration memory that may configure the programmable logic fabric. The integrated circuit device may also include a base die that may provide fabric support circuitry, including memory and/or communication interfaces as well as compute elements that may also be application-specific. The memory in the base die may be directly accessed by the programmable fabric die using a low-latency, high capacity, and high bandwidth interface.

公开(公告)号：US20190044515A1

公开(公告)日：2019-02-07

申请号：US15855419

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Ravi Prakash Gutala ,  Aravind Raghavendra Dasu ,  Sean R. Atsatt ,  Scott J. Weber

IPC: H03K19/0175 ,  G06F3/06 ,  G11C11/417 ,  H01L25/18 ,  H01L27/02 ,  H01L23/48 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00 ,  H01L23/367

Abstract: An integrated circuit device having separate dies for programmable logic fabric and circuitry to operate the programmable logic fabric are provided. A first integrated circuit die may include field programmable gate array fabric. A second integrated circuit die may be coupled to the first integrated circuit die. The second integrated circuit die may include fabric support circuitry that operates the field programmable gate array fabric of the first integrated circuit die.

公开(公告)号：US20190042127A1

公开(公告)日：2019-02-07

申请号：US15868627

申请日：2018-01-11

Applicant: Intel Corporation

Inventor： Scott J. Weber ,  David Greenhill ,  Sean R. Atsatt ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu ,  Jun Pin Tan

IPC: G06F3/06 ,  G06F12/0802

Abstract: An integrated circuit device may cache configuration data to enable rapid configuration from fabric cache memory. The integrated circuit device may include programmable logic fabric having configuration memory and programmable logic elements controlled by the configuration memory, and sector-aligned memory apart from the programmable logic fabric. A first sector of the configuration memory may be programmed with first configuration data. The sector-aligned memory may include a first sector of sector-aligned memory that may cache the first configuration data while the configuration memory is programmed with the first configuration data a first time. A second sector of sector-aligned memory may cache second configuration data for a second sector of the configuration memory in parallel while the first sector of sector-aligned memory caches the first configuration data for the first sector of the configuration memory.

公开(公告)号：US20190041923A1

公开(公告)日：2019-02-07

申请号：US15855457

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Sean R. Atsatt ,  Scott J. Weber ,  Aravind Raghavendra Dasu ,  Ravi Prakash Gutala

IPC: G06F1/20 ,  H03K19/0175 ,  H03K19/003 ,  H03K19/00 ,  G05B15/02

Abstract: An integrated circuit assembly may include an integrated circuit having a plurality of programmable logic sectors and an interposer circuit positioned adjacent to the integrated circuit. The interposer circuit may include at least one voltage regulator that distributes a voltage to at least one of the plurality of programmable logic sectors and at least one thermal sensor that measures a temperature of the at least one of the plurality of programmable logic sectors.