公开(公告)号：US20230197800A1

公开(公告)日：2023-06-22

申请号：US17556737

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Cheng-Ying Huang ,  Nicole K. Thomas ,  Marko Radosavljevic ,  Patrick Morrow ,  Ashish Agrawal ,  Willy Rachmady ,  Nazila Haratipour ,  Seung Hoon Sung

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/40 ,  H01L29/06 ,  H01L27/092

CPC classification number: H01L29/41733 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/401 ,  H01L29/0665 ,  H01L27/0922 ,  H01L29/66742

Abstract: Techniques are provided herein to form semiconductor devices having a non-reactive metal contact in an epi region of a stacked transistor configuration. An n-channel device may be located vertically above a p-channel device (or vice versa). Source or drain regions are adjacent to both ends of the n-channel device and the p-channel device, such that a source or drain region of one device is located vertically over the source or drain region of the other device. A deep and narrow contact may be formed from either the frontside or the backside of the integrated circuit through the stacked source or drain regions. According to some embodiments, the contact is formed using a refractory metal or other non-reactive metal such that no silicide or germanide is formed with the epi material of the source or drain regions at the boundary between the contact and the source or drain regions.

公开(公告)号：US20230197777A1

公开(公告)日：2023-06-22

申请号：US17556748

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Cheng-Ying Huang ,  Nicole K. Thomas ,  Marko Radosavljevic ,  Patrick Morrow ,  Ashish Agrawal ,  Willy Rachmady ,  Nazila Haratipour ,  Seung Hoon Sung ,  I-Cheng Tung ,  Christopher M. Neumann ,  Koustav Ganguly ,  Subrina Rafique

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/0665 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696

Abstract: Techniques are provided herein to form gate-all-around (GAA) semiconductor devices utilizing a metal fill in an epi region of a stacked transistor configuration. In one example, an n-channel device and the p-channel device may both be GAA transistors each having any number of nanoribbons extending in the same direction where the n-channel device is located vertically above the p-channel device (or vice versa). Source or drain regions are adjacent to both ends of the n-channel device and the p-channel device. A metal fill may be provided around the source or drain region of the bottom semiconductor device to provide a high contact area between the highly conductive metal fill and the epitaxial material of that source or drain region. Metal fill may also be used around the top source or drain region to further improve conductivity throughout both of the stacked source or drain regions.

公开(公告)号：US20230163168A1

公开(公告)日：2023-05-25

申请号：US17455938

申请日：2021-11-22

Applicant: Intel Corporation

Inventor： Ashish Agrawal ,  Christopher M. Neumann ,  Seung Hoon Sung ,  Marko Radosavljevic ,  Jack T. Kavalieros

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L29/66795 ,  H01L29/785

Abstract: Techniques are provided herein to form a forksheet device with an air gap spine. The air gap may be devoid of gas, or not. In an example, the device includes a first semiconductor body laterally extending from a first side of a void (air gap) and having an end surface that defines part of the first side of the void, and a second semiconductor body laterally extending from a second side of the void and having an end surface that defines part of the second side of the void. A first gate structure is on the first semiconductor body, and a second gate structure is on the second semiconductor body. In some cases, a spacer structure is between a source or drain region and the corresponding gate structure, the spacer structure including one or more portions of the void. The void may be created with a backside process, post-device formation.

公开(公告)号：US20230126135A1

公开(公告)日：2023-04-27

申请号：US17509223

申请日：2021-10-25

Applicant: Intel Corporation

Inventor： Christopher M. Neumann ,  Ashish Agrawal ,  Seung Hoon Sung ,  Marko Radosavljevic ,  Jack T. Kavalieros

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L27/088

Abstract: Techniques are provided herein to form a forksheet transistor device with a dielectric overhang structure. The dielectric overhang structure includes a dielectric layer that at least partially hangs over the nanoribbons of each semiconductor device in the forksheet transistor and is directly coupled to, or is an integral part of, the dielectric spine between the semiconductor devices. The overhang structure allows for a higher alignment tolerance when forming different work function metals over each of the different semiconductor devices, which in turn allows for narrower dielectric spines to be used. A first gate structure that includes a first work function metal may be formed around the nanoribbons of the n-channel device and a second gate structure that includes a second work function metal may be formed around the nanoribbons of the p-channel device in the forksheet arrangement.

公开(公告)号：US11626519B2

公开(公告)日：2023-04-11

申请号：US17074251

申请日：2020-10-19

Applicant: Intel Corporation

Inventor： Van H. Le ,  Gilbert Dewey ,  Rafael Rios ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Kent E. Millard ,  Marc C. French ,  Ashish Agrawal ,  Benjamin Chu-Kung ,  Ryan E. Arch

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L29/24 ,  H01L29/40 ,  H01L29/49 ,  H01L29/775

Abstract: Embodiments of the invention include non-planar InGaZnO (IGZO) transistors and methods of forming such devices. In an embodiment, the IGZO transistor may include a substrate and source and drain regions formed over the substrate. According to an embodiment, an IGZO layer may be formed above the substrate and may be electrically coupled to the source region and the drain region. Further embodiments include a gate electrode that is separated from the IGZO layer by a gate dielectric. In an embodiment, the gate dielectric contacts more than one surface of the IGZO layer. In one embodiment, the IGZO transistor is a finfet transistor. In another embodiment the IGZO transistor is a nanowire or a nanoribbon transistor. Embodiments of the invention may also include a non-planar IGZO transistor that is formed in the back end of line stack (BEOL) of an integrated circuit chip.

公开(公告)号：US20220328663A1

公开(公告)日：2022-10-13

申请号：US17853036

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Willy Rachmady ,  Matthew V. Metz ,  Ashish Agrawal ,  Benjamin Chu-Kung ,  Uygar E. Avci ,  Jack T. Kavalieros ,  Ian A. Young

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78

Abstract: Disclosed herein are tunneling field effect transistors (TFETs), and related methods and computing devices. In some embodiments, a TFET may include: a first source/drain material having a p-type conductivity; a second source/drain material having an n-type conductivity; a channel material at least partially between the first source/drain material and the second source/drain material, wherein the channel material has a first side face and a second side face opposite the first side face; and a gate above the channel material, on the first side face, and on the second side face.

公开(公告)号：US11462568B2

公开(公告)日：2022-10-04

申请号：US16016387

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Aaron Lilak ,  Justin Weber ,  Harold Kennel ,  Willy Rachmady ,  Gilbert Dewey ,  Van H. Le ,  Abhishek Sharma ,  Patrick Morrow ,  Ashish Agrawal

IPC: H01L27/12 ,  H01L21/8256 ,  H01L29/78 ,  H01L29/786

Abstract: Embodiments herein describe techniques for a semiconductor device including a first transistor above a substrate, an insulator layer above the first transistor, and a second transistor above the insulator layer. The first transistor includes a first channel layer above the substrate, and a first gate electrode above the first channel layer. The insulator layer is next to a first source electrode of the first transistor above the first channel layer, next to a first drain electrode of the first transistor above the first channel layer, and above the first gate electrode. The second transistor includes a second channel layer above the insulator layer, and a second gate electrode separated from the second channel layer by a gate dielectric layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20220199468A1

公开(公告)日：2022-06-23

申请号：US17133065

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Kimin Jun ,  Souvik Ghosh ,  Willy Rachmady ,  Ashish Agrawal ,  Siddharth Chouksey ,  Jessica Torres ,  Jack Kavalieros ,  Matthew Metz ,  Ryan Keech ,  Koustav Ganguly ,  Anand Murthy

IPC: H01L21/768 ,  H01L23/522 ,  H01L29/417 ,  H01L29/45 ,  H01L29/40 ,  H01L29/66 ,  H01L23/00 ,  H01L27/22 ,  H01L27/24

Abstract: An integrated circuit interconnect structure includes a metallization level above a first device level. The metallization level includes an interconnect structure coupled to the device structure, a conductive cap including an alloy of a metal of the interconnect structure and either silicon or germanium on an uppermost surface of the interconnect structure. A second device level above the conductive cap includes a transistor coupled with the conductive cap. The transistor includes a channel layer including a semiconductor material, where at least one sidewall of the conductive cap is co-planar with a sidewall of the channel layer. The transistor further includes a gate on a first portion of the channel layer, where the gate is between a source region and a drain region, where one of the source or the drain region is in contact with the conductive cap.

公开(公告)号：US11244943B2

公开(公告)日：2022-02-08

申请号：US16728983

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Gilbert Dewey ,  Ashish Agrawal ,  Kimin Jun ,  Willy Rachmady ,  Zachary Geiger ,  Cory Bomberger ,  Ryan Keech ,  Koustav Ganguly ,  Anand Murthy ,  Jack Kavalieros

IPC: H01L27/06 ,  H01L21/683 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/04 ,  H01L29/08 ,  H01L27/092

Abstract: A monolithic three-dimensional integrated circuit may include multiple transistor levels separated by one or more levels of metallization. An upper level transistor structure may include a monocrystalline channel material over a bottom gate stack. The channel material and the gate stack materials may be formed on a donor substrate at any suitable temperature, and subsequently transferred from the donor substrate to a host substrate that includes lower-level circuitry. The upper-level transistor may be patterned from the transferred layers so that the gate electrode includes one or more bonding layers. Source and drain material may be patterned from a source and drain material layer that was transferred from the donor substrate along with the channel material, or source and drain material may be grown at low temperatures from the transferred channel material.

公开(公告)号：US11164809B2

公开(公告)日：2021-11-02

申请号：US16221815

申请日：2018-12-17

Applicant: Intel Corporation

Inventor： Carl Naylor ,  Ashish Agrawal ,  Kevin Lin ,  Abhishek Sharma ,  Mauro Kobrinsky ,  Christopher Jezewski ,  Urusa Alaan

IPC: H01L27/12 ,  H01L23/40 ,  H01L21/70 ,  H01L21/822 ,  H01L23/532

Abstract: An example relates to an integrated circuit including a semiconductor substrate, and a wiring layer stack located on the semiconductor substrate. The integrated circuit further includes a transistor embedded in the wiring layer stack. The transistor includes an embedded layer. The embedded layer has a thickness of less than 10 nm. The embedded layer includes at least one two-dimensional crystalline layer including more than 10% metal atoms. Further examples relate to methods for forming integrated circuits.