公开(公告)号：US11183564B2

公开(公告)日：2021-11-23

申请号：US16015087

申请日：2018-06-21

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  Ravi Pillarisetty ,  Payam Amin ,  Roza Kotlyar ,  Patrick H. Keys ,  Hubert C. George ,  Kanwaljit Singh ,  James S. Clarke ,  David J. Michalak ,  Lester Lampert ,  Zachary R. Yoscovits ,  Roman Caudillo ,  Jeanette M. Roberts

IPC: H01L29/12 ,  H01L29/66 ,  H01L29/76 ,  H01L29/423 ,  H01L29/165 ,  H01L27/18 ,  H01L21/8234 ,  H01L29/10 ,  G06N10/00 ,  H01L39/14 ,  H01L29/06 ,  B82Y10/00 ,  H01L29/82 ,  H01L29/40 ,  H01L21/321 ,  H01L21/02 ,  H01L29/778 ,  H01L29/43

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer and a barrier layer; a first gate metal above the quantum well stack, wherein the barrier layer is between the first gate metal and the quantum well layer; and a second gate metal above the quantum well stack, wherein the barrier layer is between the second gate metal and the quantum well layer, and a material structure of the second gate metal is different from a material structure of the first gate metal.

公开(公告)号：US11063040B2

公开(公告)日：2021-07-13

申请号：US16340512

申请日：2016-12-24

Applicant: Intel Corporation

Inventor： James S. Clarke ,  Nicole K. Thomas ,  Zachary R. Yoscovits ,  Hubert C. George ,  Jeanette M. Roberts ,  Ravi Pillarisetty

IPC: H01L27/088 ,  G06N10/00 ,  H01L21/8234 ,  H01L27/18 ,  H01L29/66 ,  H01L29/778 ,  B82Y10/00

Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gates above the quantum well stack; and a plurality of second gates above the quantum well stack; wherein the plurality of first gates are arranged in electrically continuous rows extending in a first direction, and the plurality of second gates are arranged in electrically continuous rows extending in a second direction perpendicular to the first direction.

公开(公告)号：US11011693B2

公开(公告)日：2021-05-18

申请号：US16450396

申请日：2019-06-24

Applicant: Intel Corporation

Inventor： Lester Lampert ,  Ravi Pillarisetty ,  Nicole K. Thomas ,  Hubert C. George ,  Jeanette M. Roberts ,  David J. Michalak ,  Roman Caudillo ,  Thomas Francis Watson ,  Stephanie A. Bojarski ,  James S. Clarke

IPC: H01L39/04 ,  H01L39/02 ,  H01L39/22 ,  G06N10/00 ,  H01L23/552 ,  H01L27/18 ,  H01L23/46

Abstract: Embodiments of the present disclosure describe integrated quantum circuit assemblies that include quantum circuit components pre-packaged, or integrated, with some other electronic components and mechanical attachment means for easy inclusion within a cooling apparatus. An example integrated quantum circuit assembly includes a package and mechanical attachment means for securing the package within a cryogenic chamber of a cooling apparatus. The package includes a plurality of components, such as a quantum circuit component, an attenuator, and a directional coupler, which are integral to the package. Such an integrated assembly may significantly speed up installation and may help develop systems for rapidly bringing up quantum computers.

公开(公告)号：US20200373351A1

公开(公告)日：2020-11-26

申请号：US16635193

申请日：2017-09-18

Applicant: Intel Corporation

Inventor： Jeanette M. Roberts ,  Wesley T. Harrison ,  Adel A. Elsherbini ,  Stefano Pellerano ,  Zachary R. Yoscovits ,  Lester Lampert ,  Ravi Pillarisetty ,  Roman Caudillo ,  Hubert C. George ,  Nicole K. Thomas ,  David J. Michalak ,  Kanwaljit Singh ,  James S. Clarke

IPC: H01L27/18 ,  H01L39/02

Abstract: Embodiments of the present disclosure propose qubit substrates, as well as methods of fabricating thereof and related device assemblies. In one aspect of the present disclosure, a qubit substrate includes a base substrate of a doped semiconductor material, and a layer of a substantially intrinsic semiconductor material over the base substrate. Engineering a qubit substrate in this manner allows improving coherence times of qubits provided thereon, while, at the same time, being sufficiently mechanically robust so that it can be efficiently used in large-scale manufacturing.

公开(公告)号：US20200312989A1

公开(公告)日：2020-10-01

申请号：US16365018

申请日：2019-03-26

Applicant: Intel Corporation

Inventor： Hubert C. George ,  Sarah Atanasov ,  Ravi Pillarisetty ,  Lester Lampert ,  James S. Clarke ,  Nicole K. Thomas ,  Roman Caudillo ,  Kanwaljit Singh ,  David J. Michalak ,  Jeanette M. Roberts ,  Stephanie A. Bojarski

IPC: H01L29/775 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  G06N10/00

Abstract: Disclosed herein are quantum dot devices with multiple layers of gate metal, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; an insulating material above the quantum well stack, wherein the insulating material includes a trench; and a gate on the insulating material and extending into the trench, wherein the gate includes a first gate metal in the trench and a second gate metal above the first gate metal.

公开(公告)号：US20200312963A1

公开(公告)日：2020-10-01

申请号：US16367155

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Stephanie A. Bojarski ,  Hubert C. George ,  Sarah Atanasov ,  Nicole K. Thomas ,  Ravi Pillarisetty ,  Lester Lampert ,  Thomas Francis Watson ,  David J. Michalak ,  Roman Caudillo ,  Jeanette M. Roberts ,  James S. Clarke

IPC: H01L29/12 ,  H01L29/78 ,  H01L27/088 ,  H01L29/66 ,  G06N10/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack and a plurality of linear arrays of gates above the quantum well stack to control quantum dot formation in the quantum well stack. An insulating material may be between a first linear array of gates and a second linear array of gates, the insulating material may be between individual gates in the first linear array of gates, and gate metal of the first linear array of gates may extend over the insulating material.

公开(公告)号：US20190334020A1

公开(公告)日：2019-10-31

申请号：US16349955

申请日：2016-12-14

Applicant: Intel Corporation

Inventor： Payam Amin ,  Nicole K. Thomas ,  James S. Clarke ,  Jessica M. Torres ,  Ravi Pillarisetty ,  Hubert C. George ,  Kanwaljit Singh ,  Van H. Le ,  Jeanette M. Roberts ,  Roman Caudillo ,  Zachary R. Yoscovits ,  David J. Michalak

IPC: H01L29/775 ,  H01L29/12 ,  H01L29/165 ,  H01L29/66 ,  H01L21/02 ,  G06N10/00

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum processing device may include: a quantum well stack having alternatingly arranged relaxed and strained layers; and a plurality of gates disposed above the quantum well stack to control quantum dot formation in the quantum well stack.

公开(公告)号：US20190273197A1

公开(公告)日：2019-09-05

申请号：US16347097

申请日：2016-12-27

Applicant: Intel Corporation

Inventor： Jeanette M. Roberts ,  Adel A. Elsherbini ,  Shawna Liff ,  Johanna M. Swan ,  Roman Caudillo ,  Zachary R. Yoscovits ,  Nicole K. Thomas ,  Ravi Pillarisetty ,  Hubert C. George ,  James S. Clarke

IPC: H01L39/04 ,  G06N10/00 ,  H01L39/02 ,  H01L39/22 ,  H01L39/24

Abstract: One superconducting qubit device package disclosed herein includes a die having a first face and an opposing second face, and a package substrate having a first face and an opposing second face. The die includes a quantum device including a plurality of superconducting qubits and a plurality of resonators on the first face of the die, and a plurality of conductive pathways coupled between conductive contacts at the first face of the die and associated ones of the plurality of superconducting qubits or of the plurality of resonators. The second face of the package substrate also includes conductive contacts. The device package further includes first level interconnects disposed between the first face of the die and the second face of the package substrate, coupling the conductive contacts at the first face of the die with associated conductive contacts at the second face of the package substrate.

公开(公告)号：US20190221659A1

公开(公告)日：2019-07-18

申请号：US16329706

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Hubert C. George ,  James S. Clarke

IPC: H01L29/76 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7613 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/66439

Abstract: Disclosed herein are single electron transistor (SET) devices, and related methods and devices. In some embodiments, a SET device may include: first and second source/drain (S/D) electrodes; a plurality of islands, disposed between the first and second S/D electrodes; and dielectric material disposed between adjacent ones of the islands, between the first S/D electrode and an adjacent one of the islands, and between the second S/D electrode and an adjacent one of the islands.

公开(公告)号：US20190164959A1

公开(公告)日：2019-05-30

申请号：US16320773

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  Ravi Pillarisetty ,  Jeanette M. Roberts ,  Hubert C. George ,  James S. Clarke

IPC: H01L27/06 ,  G06N10/00 ,  H01L27/18 ,  H01L29/66 ,  H01L29/76 ,  H01L39/22 ,  H01L29/12 ,  H01L29/778 ,  H01L39/24

Abstract: Described herein are quantum integrated circuit (IC) assemblies that include quantum circuit components comprising a plurality of qubits and control logic coupled to the quantum circuit components and configured to control operation of those components, where the quantum circuit component(s) and the control logic are provided on a single die. By implementing control logic on the same die as the quantum circuit component(s), more functionality can be provided on-chip, thus integrating more of signal chain on-chip. Integration can greatly reduce complexity and lower the cost of quantum computing devices, reduce interfacing bandwidth, and provide an approach that can be efficiently used in large scale manufacturing. Methods for fabricating such assemblies are also disclosed.