公开(公告)号：US09355057B2

公开(公告)日：2016-05-31

申请号：US14710002

申请日：2015-05-12

Applicant: Intel Corporation

Inventor： Kok Hong Chan ,  Huimin Chen

IPC: G06F13/42 ,  G06F13/40 ,  G06F1/32

CPC classification number: G06F13/4221 ,  G06F1/3296 ,  G06F13/4022 ,  G06F13/4027 ,  G06F2213/0042 ,  G06F2213/4004 ,  Y02D10/14 ,  Y02D10/151

Abstract: A method and system for communicating data between two devices are described herein. The method detects an electrical signal of a first protocol from a first device in a repeater, wherein the first protocol comprises single-ended signaling. The method also determines the speed of the electrical signal. Additionally, the method converts the electrical signal of the first protocol into an electrical signal of a second protocol based on the speed of the electrical signal. The second protocol comprises differential signaling. Furthermore, the method sends the electrical signal of the second protocol to a second device. In addition, the method stops the electrical signal of the second protocol to the second device when the electrical signal of the second protocol indicates an end of data flow.

公开(公告)号：US09215113B1

公开(公告)日：2015-12-15

申请号：US14491484

申请日：2014-09-19

Applicant: INTEL CORPORATION

Inventor： Huimin Chen ,  Howard Heck ,  Hsiao-Ping J. Tsai

IPC: H03H7/30 ,  H03H7/40 ,  H03K5/159 ,  H04L25/03

CPC classification number: H04L25/03885 ,  G06F13/385 ,  H04L25/03343 ,  H04L25/4902

Abstract: Techniques for training a link are described herein. An example electronic device includes a port coupled to a link partner. The port and the link partner use closed-loop equalizer training to obtain receiver equalization coefficients for the receiver of the port and obtain transmitter equalization coefficients for the transmitter of the link partner.

Abstract translation: 本文描述了用于训练链接的技术。 示例性电子设备包括耦合到链路伙伴的端口。 端口和链路伙伴使用闭环均衡器训练来获得端口接收机的接收机均衡系数，并获得链路伙伴发射机的发射机均衡系数。

公开(公告)号：US11870612B2

公开(公告)日：2024-01-09

申请号：US16831650

申请日：2020-03-26

Applicant: Intel Corporation

Inventor： Huimin Chen ,  Naveed Khan ,  Tony L Lewis

IPC: H04L25/03 ,  H04L25/02

CPC classification number: H04L25/0298 ,  H04L25/0278

Abstract: Methods and apparatus for adaptive termination calibration of high-speed links. The methods provide a novel termination calibration obtained in conjunction with link training without using an external reference under which the termination resistors for transmitters (Rtx) and receivers (Rrx) are calibrated to the real channel impedance as part of the link training. The techniques may be implemented to optimize high-speed link operation in terms of impedance match between a channel's characteristic impedance and the source termination of a transmitter and the receiver termination of a receiver. During link training, both Rtx and Rrx are adjusted to maximize a peak amplitude of a received signal. Under one approach for bi-directional links, the Rrx for the receivers at both ends of the link are calibrated substantially concurrently. Under another approach, a calibrated Rrx for a first receiver is used for calibrating the Rrx for the second receiver. An Rtx may be set equal to an calibrated Rrx or may be calibrated separately.

公开(公告)号：US10915415B2

公开(公告)日：2021-02-09

申请号：US15776384

申请日：2016-10-13

Applicant: INTEL CORPORATION ,  Amit Kumar Srivastava ,  Huimin Chen

Inventor： Amit Kumar Srivastava ,  Huimin Chen

IPC: G06F11/00 ,  G06F11/273 ,  G06F11/22 ,  G06F13/42

Abstract: Techniques and mechanisms for exchanging debug information with a repeater and multiplex logic of a platform. In an embodiment, the multiplex logic can be configured to any of multiple modes including a first mode to exchange debug information between the repeater and debug client logic of the platform. Another of the multiple modes may provide an alternate communication path for exchanging functional data, other than any debug information, between the repeater and a physical layer interface of the platform. In another embodiment, the repeater is compatible with a repeater architecture identified by a universal serial bus standard. The physical layer interface is compatible with an interface specification identified by the same universal bus standard.

公开(公告)号：US20200026599A1

公开(公告)日：2020-01-23

申请号：US16506066

申请日：2019-07-09

Applicant: INTEL CORPORATION

Inventor： Huimin Chen ,  Andrew Martwick ,  Howard Heck ,  Robert Dunstan ,  Dennis Bell ,  Abdul Ismail

IPC: G06F11/10 ,  H03M5/06 ,  H03M5/12

Abstract: Techniques for encoding data are described herein. The method includes receiving a block payload at a physical layer to be transmitted via a data bus. The method includes establishing a block header comprising an arrangement of bits, the block header defining two block header types, wherein a hamming distance between block header types is at least four.

公开(公告)号：US20190042521A1

公开(公告)日：2019-02-07

申请号：US15905562

申请日：2018-02-26

Applicant: Intel Corporation

Inventor： Huimin Chen ,  Karthi Vadivelu ,  Abdul Ismail ,  Antonio Cheng ,  Nobuyuki Suzuki

IPC: G06F13/42 ,  G06F13/36 ,  G06F13/40

Abstract: A Universal Serial Bus (USB) circuitry of an apparatus is disclosed. In an example, the USB circuitry includes a High Speed (HS) transmitter to transmit data at a first data rate from the apparatus to a component; and a pair of Low Speed/Full speed (LS/FS) receivers to receive data at one or both of a second data rate or a third data rate from the component. In an example, the USB circuitry is to refrain from receiving data from the component at the first data rate.

公开(公告)号：US10108577B2

公开(公告)日：2018-10-23

申请号：US14672168

申请日：2015-03-28

Applicant: Intel Corporation

Inventor： Huimin Chen ,  Duane G. Quiet

IPC: G06F13/00 ,  G06F13/38 ,  G06F13/40 ,  G06F13/42

Abstract: A system and method is described for simplifying implementation of repeater (e.g., re-driver/re-timer) module implementation in high-data-rate interconnects that carry a relatively low-data-rate clock signal as well as the data stream (e.g., PCIe). At the endpoint, any information critical to the function of the repeater (e.g., the most recent data rate negotiated by a pair of endpoints communicating through the repeater) is embedded in the clock signal by pulse-width modulation as ordered sets. The repeater only needs to read the clock-embedded information rather than decoding the data stream. Thus repeaters for such applications reconstruct the high-rate data-stream while actually decoding only the low-rate clock signal. Because the clock-signal protocol is independent of the data-stream protocol, the repeater's operation is protocol-agnostic with respect to the data-stream.

公开(公告)号：US10061726B2

公开(公告)日：2018-08-28

申请号：US14757939

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Steven B. McGowan ,  Huimin Chen

IPC: G06F13/00 ,  G06F13/36 ,  G06F13/40 ,  H04L25/02

CPC classification number: G06F13/36 ,  G06F13/4027 ,  G06F2213/0042 ,  H04L25/0298

Abstract: A system and method of conducting precision time management in a universal serial bus system with a retimer. The method includes initiating, from the retimer, a link delay management request on an upstream-facing port of the retimer. The method further includes receiving, at a downstream-facing port of the retimer, a link delay management request and responding to the request received on the downstream-facing port.

公开(公告)号：US10019385B2

公开(公告)日：2018-07-10

申请号：US15196889

申请日：2016-06-29

Applicant: INTEL CORPORATION

Inventor： Huimin Chen

IPC: G06F13/10 ,  G06F13/16 ,  G06F13/20 ,  G06F13/42

CPC classification number: G06F13/102 ,  G06F13/16 ,  G06F13/20 ,  G06F13/4282 ,  G06F2213/0042

Abstract: Described is an apparatus comprising a first circuitry, a second circuitry, a third circuitry, and a fourth circuitry. The first circuitry may be an elastic buffer coupled to a received clock, a local clock, a received-clock data, and a local-clock data. The second circuitry may assert a first flag when a set of values on the received-clock data matches part of a skip ordered set. The third circuitry may assert a second flag when a set of values on the local-clock data matches part of the skip ordered set. The fourth circuitry may increment a count value upon assertion of the first flag and may stop incrementing the count value upon assertion of the second flag. In some embodiments, additional circuitries may extract a first timestamp from a packet, sum the first timestamp and the count value, and substitute the sum for the first timestamp within the packet.

公开(公告)号：US09959222B2

公开(公告)日：2018-05-01

申请号：US14498474

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Huimin Chen ,  Keith A. Jones ,  John L. Baudrexl ,  Ronald W. Swartz ,  Vui Yong Liew

IPC: G06F13/22 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F13/22 ,  G06F13/4054 ,  G06F13/4286

Abstract: A first state of an interconnect protocol is entered. A particular signal is sent according to the protocol to a device over a link. During the first state, it is detected that a response to the particular signal is received in the first state. It is determined that the device supports a configuration mode outside the protocol based on the received response. The configuration mode is entered based on the response. One or more in-band configuration messages are sent within the configuration mode.