-
公开(公告)号：US20220140230A1
公开(公告)日：2022-05-05
申请号：US17578093
申请日：2022-01-18
Applicant: Intel Corporation
Inventor： Sasikanth MANIPATRUNI , Kaan OGUZ , Chia-Ching LIN , Christopher WIEGAND , Tanay GOSAVI , Ian YOUNG
Abstract: An apparatus is provided which comprises: a magnetic junction including: a stack of structures including: a first structure comprising a magnet with an unfixed perpendicular magnetic anisotropy (PMA) relative to an x-y plane of a device, wherein the first structure has a first dimension along the x-y plane and a second dimension in the z-plane, wherein the second dimension is substantially greater than the first dimension. The magnetic junction includes a second structure comprising one of a dielectric or metal; and a third structure comprising a magnet with fixed PMA, wherein the third structure has an anisotropy axis perpendicular to the plane of the device, and wherein the third structure is adjacent to the second structure such that the second structure is between the first and third structures; and an interconnect adjacent to the third structure, wherein the interconnect comprises a spin orbit material.
-
32.发明申请公开(公告)号：US20200083427A1
公开(公告)日：2020-03-12
申请号：US16128426
申请日：2018-09-11
Applicant: Intel Corporation
Inventor： Sasikanth MANIPATRUNI , Kaan OGUZ , Chia-Ching LIN , Christopher WIEGAND , Tanay GOSAVI , Ian YOUNG
Abstract: An apparatus is provided which comprises: a magnetic junction including: a stack of structures including: a first structure comprising a magnet with an unfixed perpendicular magnetic anisotropy (PMA) relative to an x-y plane of a device, wherein the first structure has a first dimension along the x-y plane and a second dimension in the z-plane, wherein the second dimension is substantially greater than the first dimension. The magnetic junction includes a second structure comprising one of a dielectric or metal; and a third structure comprising a magnet with fixed PMA, wherein the third structure has an anisotropy axis perpendicular to the plane of the device, and wherein the third structure is adjacent to the second structure such that the second structure is between the first and third structures; and an interconnect adjacent to the third structure, wherein the interconnect comprises a spin orbit material.
-
Patent Agency Ranking
33.发明申请公开(公告)号：US20190378972A1
公开(公告)日：2019-12-12
申请号：US16463326
申请日：2016-12-30
Applicant: Intel Corporation
Inventor： MD Tofizur RAHMAN , Christopher J. WIEGAND , Kaan OGUZ , Daniel G. OUELLETTE , Brian MAERTZ , Kevin P. O'BRIEN , Mark L. DOCZY , Brian S. DOYLE , Oleg GOLONZKA , Tahir GHANI
Abstract: A material layer stack for a pSTTM device includes a fixed magnetic layer, a tunnel barrier disposed above the fixed magnetic layer and a free layer disposed on the tunnel barrier. The free layer further includes a stack of bilayers where an uppermost bilayer is capped by a magnetic layer including iron and where each of the bilayers in the free layer includes a non-magnetic layer such as Tungsten, Molybdenum disposed on the magnetic layer. In an embodiment, the non-magnetic layers have a combined thickness that is less than 15% of a combined thickness of the magnetic layers in the stack of bi-layers. A stack of bilayers including non-magnetic layers in the free layer can reduce the saturation magnetization of the material layer stack for the pSTTM device and subsequently increase the perpendicular magnetic anisotropy.
-
34.发明申请公开(公告)号：US20190334079A1
公开(公告)日：2019-10-31
申请号：US16463821
申请日：2016-12-30
Applicant: Intel Corporation
Inventor： MD Tofizur RAHMAN , Christopher J. WIEGAND , Kaan OGUZ , Justin S. BROCKMAN , Daniel G. OUELLETTE , Brian MAERTZ , Kevin P. O'BRIEN , Mark L. DOCZY , Brian S. DOYLE , Oleg GOLONZKA , Tahir GHANI
Abstract: A material layer stack for a pSTTM memory device includes a magnetic tunnel junction (MTJ) stack, a oxide layer, a protective layer and a capping layer. The MTJ includes a fixed magnetic layer, a tunnel barrier disposed above the fixed magnetic layer and a free magnetic layer disposed on the tunnel barrier. The oxide layer, which enables an increase in perpendicularity of the pSTTM material layer stack, is disposed on the free magnetic layer. The protective layer is disposed on the oxide layer, and acts as a protective barrier to the oxide from physical sputter damage during subsequent layer deposition. A conductive capping layer with a low oxygen affinity is disposed on the protective layer to reduce iron-oxygen de-hybridization at the interface between the free magnetic layer and the oxide layer. The inherent non-oxygen scavenging nature of the conductive capping layer enhances stability and reduces retention loss in pSTTM devices.
-
公开(公告)号：US20190280188A1
公开(公告)日：2019-09-12
申请号：US16348364
申请日：2016-12-28
Applicant: Intel Corporation
Inventor： Justin BROCKMAN , Christopher WIEGAND , MD Tofizur RAHMAN , Daniel OUELETTE , Angeline SMITH , Juan ALZATE VINASCO , Charles KUO , Mark DOCZY , Kaan OGUZ , Kevin O'BRIEN , Brian DOYLE , Oleg GOLONZKA , Tahir GHANI
Abstract: An apparatus comprises a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier between the free and fixed layers, the tunnel barrier directly contacting a first side of the free layer, a capping layer contacting the second side of the free magnetic layer and boron absorption layer positioned a fixed distance above the capping layer.
-
公开(公告)号：US20190036010A1
公开(公告)日：2019-01-31
申请号：US16072301
申请日：2016-04-01
Applicant: Intel Corporation
Inventor： Brian MAERTZ , Christopher J. WIEGAND , Daniel G. OEULLETTE , MD Tofizur RAHMAN , Oleg GOLONZKA , Justin S. BROCKMAN , Tahir GHANI , Brian S. DOYLE , Kevin P. O'BRIEN , Mark L. DOCZY , Kaan OGUZ
CPC classification number: H01L43/02 , H01L27/228 , H01L43/08 , H01L43/10 , H01L43/12
Abstract: An apparatus including an array of memory cells arranged in a grid defined by word lines and bit lines in a generally orthogonal orientation relative to one another, a memory cell including a resistive memory component and an access transistor, wherein the access transistor includes a diffusion region disposed at an acute angle relative to an associated word line. A method including etching a substrate to form a plurality of fins each including a body having a length dimension including a plurality of first junction regions and a plurality of second junction regions that are generally parallel to one another and offset by angled channel regions displacing in the length dimension an end of a first junction region from the beginning of a second junction region; removing the spacer material; and introducing a gate electrode on the channel region of each of the plurality of fins.
-
37.发明申请公开(公告)号：US20190027679A1
公开(公告)日：2019-01-24
申请号：US16070415
申请日：2016-03-30
Applicant: Intel Corporation
Inventor： Daniel G. OUELLETTE , Christopher J. WIEGAND , MD Tofizur RAHMAN , Brian MAERTZ , Oleg GOLONZKA , Justin S. BROCKMAN , Kevin P. O'BRIEN , Brian S. DOYLE , Kaan OGUZ , Tahir GHANI , Mark L. DOCZY
Abstract: Approaches for strain engineering of perpendicular magnetic tunnel junctions (pMTJs), and the resulting structures, are described. In an example, a memory structure includes a perpendicular magnetic tunnel junction (pMTJ) element disposed above a substrate. A lateral strain-inducing material layer is disposed on the pMTJ element. An inter-layer dielectric (ILD) layer is disposed laterally adjacent to both the pMTJ element and the lateral strain-inducing material layer. The ILD layer has an uppermost surface co-planar or substantially co-planar with an uppermost surface of the lateral strain-inducing material layer.
-
-
-
-
-
-
Search Results
37
records
(took 0.02 seconds)
