公开(公告)号：US20220415890A1

公开(公告)日：2022-12-29

申请号：US17359320

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Mohammad HASAN ,  Biswajeet GUHA ,  Oleg GOLONZKA ,  Leonard P. GULER ,  Leah SHOER ,  Daniel G. OUELLETTE ,  Pedro FRANCO NAVARRO ,  Tahir GHANI

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/78

Abstract: Integrated circuit structures having metal gates with tapered plugs, and methods of fabricating integrated circuit structures having metal gates with tapered plugs, are described. For example, includes a fin having a portion protruding above a shallow trench isolation (STI) structure. A gate dielectric material layer is over the protruding portion of the fin and over the STI structure. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric gate plug is laterally spaced apart from the fin. The dielectric gate plug is on the STI structure, and the dielectric gate plug has sides tapered outwardly from a top of the dielectric gate plug to a bottom of the dielectric gate plug.

公开(公告)号：US20190140166A1

公开(公告)日：2019-05-09

申请号：US16097801

申请日：2016-07-01

Applicant: MD Tofizur RAHMAN ,  Christopher J. WIEGAND ,  Brian MAERTZ ,  Daniel G. OUELLETTE ,  Kaan OGUZ ,  Brian S. DOYLE ,  Mark L. DOCZY ,  Daniel B. BERGSTROM ,  Justin S. BROCKMAN ,  Oleg GOLONZKA ,  Tahhir GHANI ,  Intel Corporation

Inventor： MD Tofizur RAHMAN ,  Christopher J. WIEGAND ,  Brian MAERTZ ,  Daniel G. OUELLETTE ,  Kevin P. O'BRIEN ,  Kaan OGUZ ,  Brian S. DOYLE ,  Mark L. DOCZY ,  Daniel B. BERGSTROM ,  Justin S. BROCKMAN ,  Oleg GOLONZKA ,  Tahir GHANI

IPC: H01L43/12 ,  H01L43/10 ,  H01L43/08 ,  H01L43/02 ,  G11C11/16

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: Material layer stack structures to provide a magnetic tunnel junction (MTJ) having improved perpendicular magnetic anisotropy (PMA) characteristics. In an embodiment, a free magnetic layer of the material layer stack is disposed between a tunnel barrier layer and a cap layer of magnesium oxide (Mg). The free magnetic layer includes a Cobalt-Iron-Boron (CoFeB) body substantially comprised of a combination of Cobalt atoms, Iron atoms and Boron atoms. A first Boron mass fraction of the CoFeB body is equal to or more than 25% (e.g., equal to or more than 27%) in a first region which adjoins an interface of the free magnetic layer with the tunnel barrier layer. In another embodiment, the first Boron mass fraction is more than a second Boron mass fraction in a second region of the CoFeB body which adjoins an interface of the free magnetic layer with the cap layer.

公开(公告)号：US20220093597A1

公开(公告)日：2022-03-24

申请号：US17030350

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Daniel G. OUELLETTE ,  Daniel B. O'BRIEN ,  Jeffrey S. LEIB ,  Orb ACTON ,  Lukas BAUMGARTEL ,  Dan S. LAVRIC ,  Dax M. CRUM ,  Oleg GOLONZKA ,  Tahir GHANI

IPC: H01L27/092 ,  H01L29/775 ,  H01L29/06 ,  H01L29/51 ,  H01L29/423 ,  H01L29/49 ,  H01L29/40

Abstract: Gate-all-around integrated circuit structures having molybdenum nitride metal gates and gate dielectrics with a dipole layer are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type conductive layer on a first gate dielectric. The P-type conductive layer includes molybdenum and nitrogen. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type conductive layer on a second gate dielectric.

公开(公告)号：US20190378972A1

公开(公告)日：2019-12-12

申请号：US16463326

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： MD Tofizur RAHMAN ,  Christopher J. WIEGAND ,  Kaan OGUZ ,  Daniel G. OUELLETTE ,  Brian MAERTZ ,  Kevin P. O'BRIEN ,  Mark L. DOCZY ,  Brian S. DOYLE ,  Oleg GOLONZKA ,  Tahir GHANI

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/10 ,  H01L43/12 ,  H01F10/32

Abstract: A material layer stack for a pSTTM device includes a fixed magnetic layer, a tunnel barrier disposed above the fixed magnetic layer and a free layer disposed on the tunnel barrier. The free layer further includes a stack of bilayers where an uppermost bilayer is capped by a magnetic layer including iron and where each of the bilayers in the free layer includes a non-magnetic layer such as Tungsten, Molybdenum disposed on the magnetic layer. In an embodiment, the non-magnetic layers have a combined thickness that is less than 15% of a combined thickness of the magnetic layers in the stack of bi-layers. A stack of bilayers including non-magnetic layers in the free layer can reduce the saturation magnetization of the material layer stack for the pSTTM device and subsequently increase the perpendicular magnetic anisotropy.

公开(公告)号：US20190334079A1

公开(公告)日：2019-10-31

申请号：US16463821

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： MD Tofizur RAHMAN ,  Christopher J. WIEGAND ,  Kaan OGUZ ,  Justin S. BROCKMAN ,  Daniel G. OUELLETTE ,  Brian MAERTZ ,  Kevin P. O'BRIEN ,  Mark L. DOCZY ,  Brian S. DOYLE ,  Oleg GOLONZKA ,  Tahir GHANI

IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  G11C11/16

Abstract: A material layer stack for a pSTTM memory device includes a magnetic tunnel junction (MTJ) stack, a oxide layer, a protective layer and a capping layer. The MTJ includes a fixed magnetic layer, a tunnel barrier disposed above the fixed magnetic layer and a free magnetic layer disposed on the tunnel barrier. The oxide layer, which enables an increase in perpendicularity of the pSTTM material layer stack, is disposed on the free magnetic layer. The protective layer is disposed on the oxide layer, and acts as a protective barrier to the oxide from physical sputter damage during subsequent layer deposition. A conductive capping layer with a low oxygen affinity is disposed on the protective layer to reduce iron-oxygen de-hybridization at the interface between the free magnetic layer and the oxide layer. The inherent non-oxygen scavenging nature of the conductive capping layer enhances stability and reduces retention loss in pSTTM devices.

公开(公告)号：US20190027679A1

公开(公告)日：2019-01-24

申请号：US16070415

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Daniel G. OUELLETTE ,  Christopher J. WIEGAND ,  MD Tofizur RAHMAN ,  Brian MAERTZ ,  Oleg GOLONZKA ,  Justin S. BROCKMAN ,  Kevin P. O'BRIEN ,  Brian S. DOYLE ,  Kaan OGUZ ,  Tahir GHANI ,  Mark L. DOCZY

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12 ,  H01L43/10

Abstract: Approaches for strain engineering of perpendicular magnetic tunnel junctions (pMTJs), and the resulting structures, are described. In an example, a memory structure includes a perpendicular magnetic tunnel junction (pMTJ) element disposed above a substrate. A lateral strain-inducing material layer is disposed on the pMTJ element. An inter-layer dielectric (ILD) layer is disposed laterally adjacent to both the pMTJ element and the lateral strain-inducing material layer. The ILD layer has an uppermost surface co-planar or substantially co-planar with an uppermost surface of the lateral strain-inducing material layer.