公开(公告)号：US20230098594A1

公开(公告)日：2023-03-30

申请号：US17484949

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Chia-Ching LIN ,  Kaan OGUZ ,  Sou-Chi CHANG ,  Arnab SEN GUPTA ,  I-Cheng TUNG ,  Ian A. YOUNG ,  Matthew V. METZ ,  Uygar E. AVCI ,  Sudarat LEE

IPC: H01G4/30 ,  H01L49/02 ,  H01G4/08 ,  H01G4/35

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related MIM capacitors that have a multiple trench structure to increase a charge density, where a dielectric of the MIM capacitor includes a perovskite-based material. In embodiments, a first electrically conductive layer may be coupled with a top metal layer of the MIM, and/or a second conductive layer may be coupled with a bottom metal layer of the MIM to reduce RC effects. Other embodiments may be described and/or claimed.

公开(公告)号：US20230097184A1

公开(公告)日：2023-03-30

申请号：US17485310

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Sarah ATANASOV ,  Nazila HARATIPOUR ,  Sou-Chi CHANG ,  Shriram SHIVARAMAN ,  Uygar E. AVCI

IPC: H01L49/02 ,  H01L27/11507

Abstract: Embodiments of the present disclosure are directed to advanced integrated circuit structure fabrication and, in particular, integrated circuits with high dielectric constant (HiK) interfacial layering between an electrode and a ferroelectric (FE) or anti-ferroelectric (AFE) layer. Other embodiments may be disclosed or claimed.

公开(公告)号：US20230090093A1

公开(公告)日：2023-03-23

申请号：US17479769

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Ashish Verma PENUMATCHA ,  Uygar E. AVCI ,  Chelsey DOROW ,  Tanay GOSAVI ,  Chia-Ching LIN ,  Carl NAYLOR ,  Nazila HARATIPOUR ,  Kevin P. O'BRIEN ,  Seung Hoon SUNG ,  Ian A. YOUNG ,  Urusa ALAAN

IPC: H01L29/423 ,  H01L29/10 ,  H01L29/08

Abstract: Thin film transistors having semiconductor structures integrated with two-dimensional (2D) channel materials are described. In an example, an integrated circuit structure includes a two-dimensional (2D) material layer above a substrate. A gate stack is above the 2D material layer, the gate stack having a first side opposite a second side. A semiconductor structure including germanium is included, the semiconductor structure laterally adjacent to and in contact with the 2D material layer adjacent the first side of the gate stack. A first conductive structure is adjacent the first side of the second gate stack, the first conductive structure over and in direct electrical contact with the semiconductor structure. The semiconductor structure is intervening between the first conductive structure and the 2D material layer. A second conductive structure is adjacent the second side of the second gate stack, the second conductive structure over and in direct electrical contact with the 2D material layer.

公开(公告)号：US20230086499A1

公开(公告)日：2023-03-23

申请号：US17479155

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Kirby MAXEY ,  Ashish Verma PENUMATCHA ,  Kevin P. O'BRIEN ,  Chelsey DOROW ,  Uygar E. AVCI ,  Sudarat LEE ,  Carl NAYLOR ,  Tanay GOSAVI

IPC: H01L29/786 ,  H01L29/78

Abstract: Thin film transistors having fin structures integrated with two-dimensional (2D) channel materials are described. In an example, an integrated circuit structure includes a plurality of insulator fins above a substrate. A two-dimensional (2D) material layer is over the plurality of insulator fins. A gate dielectric layer is on the 2D material layer. A gate electrode is on the gate dielectric layer. A first conductive contact is on the 2D material layer adjacent to a first side of the gate electrode. A second conductive contact is on the 2D material layer adjacent to a second side of the gate electrode, the second side opposite the first side.

公开(公告)号：US20220199756A1

公开(公告)日：2022-06-23

申请号：US17133105

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： I-Cheng TUNG ,  Kaan OGUZ ,  Chia-Ching LIN ,  Sou-Chi CHANG ,  Matthew V. METZ ,  Uygar E. AVCI

IPC: H01L49/02 ,  H01L23/522 ,  H01L29/24 ,  H01L29/786 ,  H01L29/66

Abstract: Metal insulator metal capacitors or backend transistors having epitaxial oxides are described. In a first example, metal-insulator-metal (MIM) capacitor includes a first electrode plate. A capacitor dielectric is on the first electrode plate. The capacitor dielectric includes a single crystalline oxide material. A second electrode plate is on the capacitor dielectric, the second electrode plate having a portion over and parallel with the first electrode plate. In a second example, a transistor includes a gate electrode above a substrate. A gate dielectric above and on the gate electrode. The gate dielectric includes a single crystalline oxide material. A channel material layer is on the single crystalline oxide material. Source or drain contacts are on the channel material layer.

公开(公告)号：US20220199519A1

公开(公告)日：2022-06-23

申请号：US17129854

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Chia-Ching LIN ,  Sou-Chi CHANG ,  Kaan OGUZ ,  I-Cheng TUNG ,  Arnab SEN GUPTA ,  Ian A. YOUNG ,  Uygar E. AVCI ,  Matthew V. METZ ,  Ashish Verma PENUMATCHA ,  Anandi ROY

IPC: H01L23/522 ,  H01L49/02

Abstract: Metal insulator metal capacitors are described. In an example, a metal-insulator-metal (MIM) capacitor includes a first electrode plate, and a first capacitor dielectric on the first electrode plate. The first capacitor dielectric is or includes a perovskite high-k dielectric material. A second electrode plate is on the first capacitor dielectric and has a portion over and parallel with the first electrode plate, and a second capacitor dielectric is on the second electrode plate. A third electrode plate is on the second capacitor dielectric and has a portion over and parallel with the second electrode plate.

公开(公告)号：US20220149192A1

公开(公告)日：2022-05-12

申请号：US17093452

申请日：2020-11-09

Applicant: Intel Corporation

Inventor： Kirby MAXEY ,  Ashish Verma PENUMATCHA ,  Carl NAYLOR ,  Chelsey DOROW ,  Kevin P. O'BRIEN ,  Shriram SHIVARAMAN ,  Tanay GOSAVI ,  Uygar E. AVCI ,  Sudarat LEE

IPC: H01L29/76 ,  H01L29/24 ,  H01L29/786 ,  H01L29/66

Abstract: Thin film transistors having electrostatic double gates are described. In an example, an integrated circuit structure includes an insulator layer above a substrate. A first gate stack is on the insulator layer. A 2D channel material layer is on the first gate stack. A second gate stack is on a first portion of the 2D channel material layer, the second gate stack having a first side opposite a second side. A first conductive contact is adjacent the first side of the second gate stack, the first conductive contact on a second portion of the 2D channel material layer. A second conductive contact is adjacent the second side of the second gate stack, the second conductive contact on a third portion of the 2D channel material layer. A gate electrode of the first gate stack extends beneath a portion of the first conductive contact and beneath a portion of the second conductive contact.

公开(公告)号：US20210159228A1

公开(公告)日：2021-05-27

申请号：US17142176

申请日：2021-01-05

Applicant: Intel Corporation

Inventor： Peter L.D. CHANG ,  Uygar E. AVCI ,  David KENCKE ,  Ibrahim BAN

IPC: H01L27/108 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/16

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

公开(公告)号：US20200321446A1

公开(公告)日：2020-10-08

申请号：US16635739

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Seiyon KIM ,  Uygar E. AVCI ,  Joshua M. HOWARD ,  Ian A. YOUNG ,  Daniel H. MORRIS

IPC: H01L29/66 ,  H01L29/51

Abstract: Field effect transistors having a ferroelectric or antiferroelectric gate dielectric structure are described. In an example, an integrated circuit structure includes a semiconductor channel structure includes a monocrystalline material. A gate dielectric is over the semiconductor channel structure. The gate dielectric includes a ferroelectric or antiferroelectric polycrystalline material layer. A gate electrode has a conductive layer on the ferroelectric or antiferroelectric polycrystalline material layer, the conductive layer including a metal. A first source or drain structure is at a first side of the gate electrode. A second source or drain structure is at a second side

公开(公告)号：US20200312854A1

公开(公告)日：2020-10-01

申请号：US16900359

申请日：2020-06-12

Applicant: Intel Corporation

Inventor： Peter L.D. CHANG ,  Uygar E. AVCI ,  David KENCKE ,  Ibrahim BAN

IPC: H01L27/108 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/16

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.