公开(公告)号：US06477635B1

公开(公告)日：2002-11-05

申请号：US09435862

申请日：1999-11-08

申请人： James Allan Kahle ,  George McNeil Lattimore ,  Jose Angel Paredes ,  Larry Edward Thatcher

发明人： James Allan Kahle ,  George McNeil Lattimore ,  Jose Angel Paredes ,  Larry Edward Thatcher

IPC分类号： G06F1210

CPC分类号： G06F12/1063 ,  G06F12/0831 ,  G06F12/0897

摘要： A data processing system including a processor having a load/store unit and a method for correcting effective address aliasing. In the load/store unit within the processor, load and store instructions are executed out of order. The load and store instructions are assigned tags in a predetermined manner, and then assigned to load and store reorder queues for keeping track of the program order of the load and store instructions. A real address tag is utilized to correct for effective address aliasing within the load/store unit.

摘要翻译： 一种数据处理系统，包括具有加载/存储单元的处理器和用于校正有效地址混叠的方法。 在处理器内的加载/存储单元中，加载和存储指令按顺序执行。 加载和存储指令以预定方式分配标签，然后分配给加载和存储重新排序队列，以跟踪加载和存储指令的程序顺序。 利用真实地址标签来校正加载/存储单元内的有效地址混叠。

公开(公告)号：US06298436B1

公开(公告)日：2001-10-02

申请号：US09327644

申请日：1999-06-08

申请人： James Allan Kahle ,  Hung Qui Le ,  Larry Edward Thatcher ,  David James Shippy

发明人： James Allan Kahle ,  Hung Qui Le ,  Larry Edward Thatcher ,  David James Shippy

IPC分类号： G06F9305

CPC分类号： G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/3842

摘要： A method and system for atomic memory accesses in a processor system, wherein the processor system is able to issue and execute multiple instructions out of order with respect to a particular program order. A first reservation instruction is speculatively issued to an execution unit of the processor system. Upon issuance, instructions queued for the execution unit which occur after the first reservation instruction in the program order are flushed from the execution unit, in response to detecting any previously executed reservation instructions in the execution unit which occur after the first reservation instruction in the program order. The first reservation instruction is speculatively executed by placing a reservation for a particular data address of the first reservation instruction, in response to completion of instructions queued for the execution unit which occur prior to the first reservation instruction in the program order, such that reservation instructions which are speculatively issued and executed in any order are executed in-order with respect to a partnering conditional store instruction.

摘要翻译： 一种用于处理器系统中的原子存储器访问的方法和系统，其中所述处理器系统能够相对于特定程序顺序发出并执行不正常的多个指令。 推测性地向处理器系统的执行单元发出第一预约指令。 在发行时，响应于在程序中的第一预约指令之后发生的执行单元中检测到任何先前执行的预定指令而从执行单元中刷新在程序顺序中的第一预约指令之后发生的执行单元排队的指令 订购。 响应于在程序顺序中的第一预约指令之前发生的执行单元排队的指令的完成，通过对第一预约指令的特定数据地址进行预约来推测地执行第一预约指令，使得预约指令 相对于合作条件存储指令，以任何顺序被推测地发行和执行的这些被按顺序执行。

公开(公告)号：US06209081B1

公开(公告)日：2001-03-27

申请号：US08255130

申请日：1994-06-07

申请人： James Allan Kahle ,  Donald Emil Waldecker

发明人： James Allan Kahle ,  Donald Emil Waldecker

IPC分类号： G06F1500

CPC分类号： G06F9/3838 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3861 ,  G06F9/3863

摘要： A method and system for permitting nonsequential instruction dispatch in a superscalar processor system which dispatches sequentially ordered multiple instructions simultaneously to a group of execution units on an opportunistic basis for execution and placement of results thereof within specified general purpose registers. Each instruction generally includes at least one source operand and one destination operand. A plurality of intermediate storage buffers are provided and each time an instruction is dispatched to an available execution unit, a particular one of the intermediate storage buffers is assigned to any destination operand within the dispatched instruction, permitting the results of the execution of each instruction to be stored within an intermediate storage buffer. An indication of the status of each instruction is maintained within a completion buffer and thereafter utilized to selectively transfer results within the intermediate storage buffers to selected general purpose registers in an order consistent with an application specified sequential order. The occurrence of an interrupt which prohibits completion of a selected instruction can therefore be accurately identified within the completion buffer.

摘要翻译： 一种用于在超标量处理器系统中允许非顺序指令调度的方法和系统，其在机会性的基础上将顺序排列的多个指令同时分派到一组执行单元，以便在指定的通用寄存器内执行和将其结果放置。 每个指令通常包括至少一个源操作数和一个目的操作数。 提供多个中间存储缓冲器，并且每当将指令分派到可用的执行单元时，中间存储缓冲器中的特定一个被分配给调度指令内的任何目的地操作数，从而允许执行每个指令的结果 存储在中间存储缓冲区中。 每个指令的状态的指示保持在完成缓冲器内，然后用于以与应用指定的顺序顺序一致的顺序将中间存储缓冲器内的结果选择性地传送到所选通用寄存器。 因此，可以在完成缓冲器内准确地识别出禁止完成所选指令的中断的发生。

公开(公告)号：US5978896A

公开(公告)日：1999-11-02

申请号：US289801

申请日：1994-08-12

申请人： James Allan Kahle ,  Chin-Cheng Kau ,  David Steven Levitan ,  Aubrey Deene Ogden

发明人： James Allan Kahle ,  Chin-Cheng Kau ,  David Steven Levitan ,  Aubrey Deene Ogden

IPC分类号： G06F9/38

CPC分类号： G06F9/3814 ,  G06F9/3802 ,  G06F9/3885

摘要： A method and system for increased instruction dispatch efficiency in a superscalar processor system having an instruction queue for receiving a group of instructions in an application specified sequential order and an instruction dispatch unit for dispatching instructions from an associated instruction buffer to multiple execution units on an opportunistic basis. The dispatch status of instructions within the associated instruction buffer is periodically determined and, in response to a dispatch of the instructions at the beginning of the instruction buffer, the remaining instructions are shifted within the instruction buffer in the application specified sequential order and a partial group of instructions are loaded into the instruction buffer from the instruction queue utilizing a selectively controlled multiplex circuit. In this manner additional instructions may be dispatched to available execution units without requiring a previous group of instructions to be dispatched completely.

摘要翻译： 一种用于在具有指令队列的超标量处理器系统中提高指令调度效率的方法和系统，所述指令队列用于以应用指定的顺序顺序接收一组指令，以及指令调度单元，用于将指令从相关联的指令缓冲器分派到多个执行单元， 基础。 周期性地确定关联指令缓冲器内的指令的调度状态，并且响应于在指令缓冲器的开始处的指令的调度，剩余的指令在应用指定的顺序顺序的指令缓冲器内移动，部分组 的指令通过选择性控制的多路复用电路从指令队列加载到指令缓冲器中。 以这种方式，可以将附加指令分派到可用的执行单元，而不需要完全调度先前的指令组。

公开(公告)号：US5930484A

公开(公告)日：1999-07-27

申请号：US933156

申请日：1997-09-18

申请人： Cang Ngoc Tran ,  James Allan Kahle

发明人： Cang Ngoc Tran ,  James Allan Kahle

IPC分类号： G06F13/40 ,  G06F13/14 ,  G06F13/00

CPC分类号： G06F13/4018

摘要： A method and system for input/output control in a multiprocessor system having multiprocessors coupled to a system memory via a common wide bus. The common wide bus is subdivided into multiple sub-buses which may be accessed individually or in groups by a selected processor, or individual sub-buses may be accessed by multiple processors simultaneously in response to one or more transfer requests. In response to a transfer request having a data address associated therewith, a particular target device is identified. The data address is then written into an address queue. Thereafter, one or more of the multiple sub-buses are utilized to transfer data to or from a single processor in response to a transfer request from a single processor. In response to a transfer request from multiple processors, one or more of the multiple sub-buses may be utilized separately to simultaneously transfer data to or from multiple processors.

摘要翻译： 一种具有通过公共宽总线耦合到系统存储器的多处理器的多处理器系统中的输入/输出控制的方法和系统。 公共宽总线被细分为多个子总线，可以由所选择的处理器单独访问或分组访问，或者响应于一个或多个传送请求，可以由多个处理器同时访问各个子总线。 响应于具有与其相关联的数据地址的传送请求，识别特定的目标设备。 然后将数据地址写入地址队列。 此后，响应于来自单个处理器的传送请求，利用多个子总线中的一个或多个将数据传送到单个处理器或从单个处理器传送数据。 响应于来自多个处理器的传送请求，可以单独使用多个子总线中的一个或多个，以同时向多个处理器传送数据或从多个处理器传送数据。

公开(公告)号：US5761473A

公开(公告)日：1998-06-02

申请号：US1863

申请日：1993-01-08

申请人： James Allan Kahle ,  Chin-Cheng Kau

发明人： James Allan Kahle ,  Chin-Cheng Kau

IPC分类号： G06F9/38 ,  G06F9/345

CPC分类号： G06F9/3838

摘要： A method and system for increased instruction synchronization efficiency in a superscalar processor system which includes instructions having multiple source and destination operands. Simultaneous dispatching of multiple instructions creates a source-to-destination data dependency problem in that the results of one instruction may be necessary to accomplish execution of a second instruction. Data dependency hazards may be eliminated by prohibiting each instruction from dispatching until all possible data dependencies have been eliminated by the completion of preceding instructions; however, instruction dispatch efficiency is substantially decreased utilizing this technique. Data dependency interlock circuitry may be utilized to clear possible data dependency hazards; however, the complexity of such circuitry increases dramatically as the number of interlocked sources and destinations increases. The method and system of the present invention utilizes data dependency interlock circuitry capable of interlocking two source operands by two destination operands for each instruction. Instructions having three or more source operands are interlocked at the dispatch stage for the first two source operands utilizing existing data dependency interlock circuitry. Thereafter, the instruction is dispatched only after data dependency hazards are cleared for the first two source operands, utilizing the data dependency interlock circuitry, and all instructions preceding the instruction have been completed, eliminating possible data dependency hazards for the third source operand. In this manner, instructions which include three source operands may be synchronized without requiring a substantial increase in data dependency interlock circuitry and with only a slight degradation in system efficiency.

摘要翻译： 一种用于在包括具有多个源和目的地操作数的指令的超标量处理器系统中提高指令同步效率的方法和系统。 多个指令的同时调度会产生源对目标数据依赖性问题，因为一个指令的结果可能需要完成第二个指令的执行。 可以通过禁止每个指令进行调度直到所有可能的数据相关性已经通过完成前面的指令而被消除来消除数据依赖危害; 然而，利用这种技术，指令调度效率显着降低。 可以利用数据依赖互锁电路来清除可能的数据依赖危害; 然而，随着互锁源和目的地的数量的增加，这种电路的复杂性急剧增加。 本发明的方法和系统利用数据相关互锁电路，其能够通过用于每个指令的两个目的地操作数来互锁两个源操作数。 具有三个或更多个源操作数的指令在使用现有数据依赖性互锁电路的前两个源操作数的调度阶段互锁。 此后，只有在前两个源操作数的数据依赖性危险被清除之后，才使用数据相关联锁电路来调度指令，并且完成了指令之前的所有指令，从而消除了对第三源操作数的可能的数据依赖性危害。 以这种方式，包括三个源操作数的指令可以被同步，而不需要数据依赖性联锁电路的显着增加，并且只有系统效率的轻微降低。

公开(公告)号：US08051315B2

公开(公告)日：2011-11-01

申请号：US12269997

申请日：2008-11-13

申请人： James Allan Kahle ,  David J. Shippy ,  Albert James Van Norstrand, Jr.

发明人： James Allan Kahle ,  David J. Shippy ,  Albert James Van Norstrand, Jr.

IPC分类号： G06F1/32

CPC分类号： G06F9/30112 ,  G06F1/3203 ,  G06F1/3287 ,  G06F9/30141 ,  G06F9/30189 ,  Y02D10/171 ,  Y02D50/20

摘要： Disclosed is an apparatus which deactivates both the AC as well as the DC component of power for various functions in a CPU. The CPU partitions dataflow registers and arithmetic units such that voltage can be removed from the upper portion of dataflow registers when the software is not utilizing same. Clock signals are also prevented from being applied to these non-utilized components. As an example, if a 64 bit CPU (processor unit) is to be used with both 32 and 64 bit software, the mentioned components may be partitioned in equal sized upper and lower portions. The logic signal for activating the removal of voltage may be obtained from a software-accessible architected control register designated as a machine state register in some CPUs. The same logic may be used in connection with removing voltage and clocks from other specialized functional components such as the floating point unit when software instructions do not presently require same.

摘要翻译： 公开了一种对CPU中的各种功能的AC以及DC分量进行停用的装置。 CPU分配数据流寄存器和算术单元，使得当软件不使用相同时，可以从数据流寄存器的上部去除电压。 还防止时钟信号被施加到这些未使用的组件。 作为示例，如果要使用32位和64位软件的64位CPU（处理器单元），则所提到的组件可以被分成相同大小的上部和下部。 用于激活电压去除的逻辑信号可以从在某些CPU中指定为机器状态寄存器的软件可访问的架构控制寄存器获得。 当软件指令当前不需要相同时，相同的逻辑可用于从其他专门功能组件（例如浮点单元）中去除电压和时钟。

公开(公告)号：US07720982B2

公开(公告)日：2010-05-18

申请号：US11716845

申请日：2007-03-12

申请人： Masakazu Suzuoki ,  Takeshi Yamazaki ,  Harm Peter Hofstee ,  Martin E. Hopkins ,  Charles Ray Johns ,  James Allan Kahle ,  Shigehiro Asano ,  Atsushi Kunimatsu

发明人： Masakazu Suzuoki ,  Takeshi Yamazaki ,  Harm Peter Hofstee ,  Martin E. Hopkins ,  Charles Ray Johns ,  James Allan Kahle ,  Shigehiro Asano ,  Atsushi Kunimatsu

IPC分类号： G06F15/16

CPC分类号： G06F9/4862 ,  G06F15/16 ,  H04L29/06027 ,  H04L63/168 ,  H04L67/10 ,  H04L67/34

摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.

摘要翻译： 提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。 该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。 公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。 还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。 提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。 统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。 每个软件单元在网络上唯一标识。 还提供了一种用于创建用于处理流数据的专用流水线的系统和方法。

公开(公告)号：US07496673B2

公开(公告)日：2009-02-24

申请号：US11065707

申请日：2005-02-24

申请人： Michael Karl Gschwind ,  Harm Peter Hofstee ,  Martin E. Hopkins ,  James Allan Kahle

发明人： Michael Karl Gschwind ,  Harm Peter Hofstee ,  Martin E. Hopkins ,  James Allan Kahle

IPC分类号： G06F15/16

CPC分类号： G06F9/4862 ,  G06F15/16 ,  H04L29/06027 ,  H04L63/168 ,  H04L67/10 ,  H04L67/34

摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

摘要翻译： 提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。 该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。 公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。 还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。 提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。 统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。 每个软件单元在网络上唯一标识。

公开(公告)号：US20080256275A1

公开(公告)日：2008-10-16

申请号：US12049323

申请日：2008-03-15

申请人： Harm Peter Hofstee ,  Charles Ray Johns ,  James Allan Kahle

发明人： Harm Peter Hofstee ,  Charles Ray Johns ,  James Allan Kahle

IPC分类号： G06F13/00

CPC分类号： G06F9/4862 ,  G06F15/16 ,  H04L29/06027 ,  H04L63/168 ,  H04L67/10 ,  H04L67/34

摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

摘要翻译： 提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。 该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。 公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。 还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。 提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。 统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。 每个软件单元在网络上唯一标识。