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46 条记录 (耗时 0.057 秒)

    Stage having controlled variable resistance load circuit for use in voltage controlled ring oscillator
    32.
    发明授权
    Stage having controlled variable resistance load circuit for use in voltage controlled ring oscillator 有权
    具有控制可变电阻负载电路的阶段用于压控环形振荡器

    公开(公告)号：US06198357B1

    公开(公告)日：2001-03-06

    申请号：US09153014

    申请日：1998-09-14

    申请人： James E. O'Toole ,  John R. Tuttle ,  Mark E. Tuttle ,  Tyler Lowrey ,  Kevin M. Devereaux ,  George E. Pax ,  Brian P. Higgins ,  David K. Ovard ,  Shu-Sun Yu ,  Robert R. Rotzoll

    发明人： James E. O'Toole ,  John R. Tuttle ,  Mark E. Tuttle ,  Tyler Lowrey ,  Kevin M. Devereaux ,  George E. Pax ,  Brian P. Higgins ,  David K. Ovard ,  Shu-Sun Yu ,  Robert R. Rotzoll

    IPC分类号： H03B502

    CPC分类号： G06K19/0716 ,  G06K7/0008 ,  G06K7/10059 ,  G06K19/0707 ,  G06K19/0712 ,  G06K19/0723 ,  G06K19/0726 ,  G06K19/07749 ,  G06K19/07758 ,  G06K2017/0051 ,  H01Q1/2225 ,  H03L7/0995 ,  H03L7/148

    摘要： A stage for a ring oscillator, the stage including a first p-channel transistor having a gate defining a control node, having a source adapted to be coupled to a supply voltage, and having a drain; a second p-channel transistor having a gate coupled to the control node, having a source coupled to the supply voltage, and having a drain; a first n-channel transistor having a gate defining a first input, having a drain coupled to the drain of the first p-channel transistor and defining a first node, and having a source; a second n-channel transistor having a gate defining a second input, having a drain coupled to the drain of the second p-channel transistor and defining a second node, and having a source; a current source coupled to the sources of the first and second n-channel transistors directing current from the sources of the first and second n-channel transistors; a first resistor coupled between the supply voltage and the drain of the first n-type transistor; a second resistor coupled between the supply voltage and drain of the second n-type transistor; a first source follower having an input coupled to the first node and having an output defining a first output of the stage; and a second source follower having an input coupled to the second node and having an output defining a second output of the stage.

    摘要翻译： 用于环形振荡器的级，该级包括具有限定控制节点的栅极的第一p沟道晶体管，其具有适于耦合到电源电压并具有漏极的源极; 第二p沟道晶体管，其具有耦合到所述控制节点的栅极，具有耦合到所述电源电压的源极并具有漏极; 第一n沟道晶体管，其具有限定第一输入的栅极，具有耦合到第一p沟道晶体管的漏极并限定第一节点并具有源极的漏极; 具有限定第二输入的栅极的第二n沟道晶体管，具有耦合到所述第二p沟道晶体管的漏极并限定第二节点并具有源极的漏极; 耦合到所述第一和第二n沟道晶体管的源极的电流源，其引导来自所述第一和第二n沟道晶体管的源极的电流; 耦合在第一n型晶体管的电源电压和漏极之间的第一电阻器; 耦合在第二n型晶体管的电源电压和漏极之间的第二电阻器; 第一源跟随器，具有耦合到所述第一节点并具有定义所述级的第一输出的输出的输入; 以及第二源极跟随器，其具有耦合到所述第二节点并且具有限定所述平台的第二输出的输出的输入。

    Digital clock recovery loop
    34.
    发明授权
    Digital clock recovery loop 有权
    数字时钟恢复回路

    公开(公告)号：US06285261B1

    公开(公告)日：2001-09-04

    申请号：US09610177

    申请日：2000-07-05

    申请人： George E. Pax ,  James E. O'Toole ,  Dan M. Griffin

    发明人： George E. Pax ,  James E. O'Toole ,  Dan M. Griffin

    IPC分类号： H03L100

    CPC分类号： H03L7/0895 ,  H03L7/0896 ,  H03L7/113 ,  H04B1/707 ,  H04L7/033

    摘要： A method of using a phase lock loop to receive an oscillating input signal and produce an output signal, the phase lock loop comprising a plurality of flip-flops which are chained together, the plurality of flip-flops including a first flip-flop having a first output, including a second flip-flop having an input coupled to the first output and having a second output, and including a third flip-flop having an input coupled to the second output, the phase lock loop further comprising a control node, the method including using the flip-flops to determine time spacing between transitions to perform a frequency comparison of the output signal relative to the input signal; extracting a clock from an input digital signal; and performing phase control and adjusting the voltage on the control node of the voltage controlled oscillator.

    摘要翻译： 一种使用锁相环接收振荡输入信号并产生输出信号的方法，所述锁相环包括链接在一起的多个触发器，所述多个触发器包括具有第一触发器的第一触发器， 第一输出，包括具有耦合到第一输出并具有第二输出的输入的第二触发器，并且包括具有耦合到第二输出的输入的第三触发器，所述锁相环还包括控制节点， 方法，包括使用触发器来确定转变之间的时间间隔以执行输出信号相对于输入信号的频率比较; 从输入数字信号中提取时钟; 并执行相位控制和调节压控振荡器的控制节点上的电压。

    Digital clock recovery loop
    35.
    发明授权
    Digital clock recovery loop 失效
    数字时钟恢复回路

    公开(公告)号：US5774022A

    公开(公告)日：1998-06-30

    申请号：US707220

    申请日：1996-08-29

    申请人： Dan M. Griffin ,  George E. Pax ,  James E. O'Toole

    发明人： Dan M. Griffin ,  George E. Pax ,  James E. O'Toole

    IPC分类号： H03L7/089 ,  H03L7/113 ,  H04B1/707 ,  H04L7/033 ,  H03L7/10

    CPC分类号： H03L7/113 ,  H03L7/0895 ,  H03L7/0896 ,  H04L7/033 ,  H04B1/707

    摘要： A communications system including a clock recovery circuit that extracts a clock signal from incoming digital data, the clock recovery circuit including a voltage controlled oscillator having a control node and having an output producing an output wave having a frequency that varies in response to a voltage applied to the control node; charge pump and loop filter circuitry that controls the rate of change of the voltage on the control node of the voltage controlled oscillator; a start-up circuit that performs frequency detection and, in conjunction with the charge pump and loop filter circuitry, adjusts the voltage on the control node of the voltage controlled oscillator; and a state machine that performs phase detection and adjusts the voltage on the control node of the voltage controlled oscillator.

    摘要翻译： 一种通信系统，包括从输入数字数据中提取时钟信号的时钟恢复电路，所述时钟恢复电路包括具有控制节点的压控振荡器，并具有产生具有响应于施加的电压而变化的频率的输出波的输出 到控制节点; 电荷泵和环路滤波器电路，用于控制压控振荡器的控制节点上的电压变化率; 启动电路，执行频率检测，并结合电荷泵和环路滤波器电路调节压控振荡器的控制节点上的电压; 以及执行相位检测并调节压控振荡器的控制节点上的电压的状态机。

    Digital clock recovery loop
    36.
    发明授权
    Digital clock recovery loop 有权
    数字时钟恢复回路

    公开(公告)号：US06100765A

    公开(公告)日：2000-08-08

    申请号：US397484

    申请日：1999-09-16

    申请人： George E. Pax ,  James E. O'Toole

    发明人： George E. Pax ,  James E. O'Toole

    IPC分类号： H03L7/089 ,  H03L7/113 ,  H04B1/707 ,  H04L7/033 ,  H03L1/00 ,  H03L7/18 ,  H03L7/89

    CPC分类号： H03L7/0895 ,  H03L7/0896 ,  H03L7/113 ,  H04L7/033 ,  H04B1/707

    摘要： A communications system including a clock recovery circuit that extracts a clock signal from incoming digital data, the clock recovery circuit comprising: a voltage controlled oscillator having a control node and an output producing an output wave having a frequency that varies in response to a voltage applied to the control node; charge pump and loop filter circuitry that controls the rate of change of the voltage on the control node of the voltage controlled oscillator; a start-up circuit that performs frequency detection and, in conjunction with the charge pump and loop filter circuitry, adjusts the voltage on the control node of the voltage controlled oscillator; and a state machine that performs phase detection and adjusts the voltage on the control node of the voltage controlled oscillator.

    摘要翻译： 一种包括从输入数字数据提取时钟信号的时钟恢复电路的通信系统，所述时钟恢复电路包括：压控振荡器，具有控制节点和产生具有响应于施加电压而变化的频率的输出波的输出 到控制节点; 电荷泵和环路滤波器电路，用于控制压控振荡器的控制节点上的电压变化率; 启动电路，执行频率检测，并结合电荷泵和环路滤波器电路调节压控振荡器的控制节点上的电压; 以及执行相位检测并调节压控振荡器的控制节点上的电压的状态机。

    Digital clock recovery loop
    37.
    发明授权
    Digital clock recovery loop 失效
    数字时钟恢复回路

    公开(公告)号：US5982237A

    公开(公告)日：1999-11-09

    申请号：US5090

    申请日：1998-01-09

    申请人： George E. Pax ,  James E. O'Toole ,  Dan M. Griffin

    发明人： George E. Pax ,  James E. O'Toole ,  Dan M. Griffin

    IPC分类号： H03L7/089 ,  H03L7/113 ,  H04B1/707 ,  H04L7/033 ,  H03L1/00 ,  H03L7/18

    CPC分类号： H03L7/113 ,  H03L7/0895 ,  H03L7/0896 ,  H04L7/033 ,  H04B1/707

    摘要： A communications system including a clock recovery circuit that extracts a clock signal from incoming digital data, the clock recovery circuit comprising:a voltage controlled oscillator having a control node and having an output producing an output wave having a frequency that varies in response to a voltage applied to the control node; charge pump and loop filter circuitry that controls the rate of change of the voltage on the control node of the voltage controlled oscillator; a start-up circuit that performs frequency detection and, in conjunction with the charge pump and loop filter circuitry, adjusts the voltage on the control node of the voltage controlled oscillator; and a state machine that performs phase detection and adjusts the voltage on the control node of the voltage controlled oscillator.

    摘要翻译： 一种通信系统，包括从输入的数字数据中提取时钟信号的时钟恢复电路，所述时钟恢复电路包括：具有控制节点并具有产生具有响应于电压而变化的频率的输出波的输出的压控振荡器 应用于控制节点; 电荷泵和环路滤波器电路，用于控制压控振荡器的控制节点上的电压变化率; 启动电路，执行频率检测，并结合电荷泵和环路滤波器电路调节压控振荡器的控制节点上的电压; 以及执行相位检测并调节压控振荡器的控制节点上的电压的状态机。

    Forced substrate test mode for packaged integrated circuits
    38.
    发明授权
    Forced substrate test mode for packaged integrated circuits 失效
    用于封装集成电路的强制衬底测试模式

    公开(公告)号：US5212442A

    公开(公告)日：1993-05-18

    申请号：US854485

    申请日：1992-03-20

    申请人： James E. O'Toole ,  Brian P. Higgins

    发明人： James E. O'Toole ,  Brian P. Higgins

    IPC分类号： G01R31/30 ,  G01R31/317 ,  G11C29/50

    CPC分类号： G01R31/30 ,  G01R31/31701 ,  G11C29/50 ,  G11C11/401 ,  G11C11/41

    摘要： An integrated circuit such as an SRAM or DRAM fabricated in a package having a number of external pins includes a plurality of inputs and outputs electrically coupled to the external package pins, an internal substrate that is unconnected to any of the external pins, a test mode indicator circuit having an input coupled to an external pin and an output for providing a test mode signal and a switch responsive to the test mode signal for coupling the substrate to a predetermined voltage. The predetermined voltage can either be ground, or a negative voltage introduced on a pin that is normally set to a logic zero during package level testing. The test mode signal can also be used to disable the on-chip charge pump. The test mode indicator circuit can include a super voltage indicator, an electronic key, or latch circuit in order to receive the test mode indication signal on an existing package pin.

    摘要翻译： 在具有多个外部引脚的封装中制造的诸如SRAM或DRAM的集成电路包括电耦合到外部封装引脚的多个输入和输出，未连接到任何外部引脚的内部基板，测试模式 指示器电路具有耦合到外部引脚的输入和用于提供测试模式信号的输出和响应于测试模式信号的开关，用于将基板耦合到预定电压。 预定电压可以被接地，也可以是在封装级测试期间通常设置为逻辑0的引脚上的负电压。 测试模式信号也可用于禁用片上电荷泵。 测试模式指示器电路可以包括超电压指示器，电子钥匙或锁存电路，以便在现有封装引脚上接收测试模式指示信号。

    Depletion mode chip decoupling capacitor
    39.
    发明授权
    Depletion mode chip decoupling capacitor 失效
    耗尽模式芯片去耦电容

    公开(公告)号：US5032892A

    公开(公告)日：1991-07-16

    申请号：US453861

    申请日：1989-12-20

    申请人： Wen-Foo Chern ,  Ward M. Parkinson ,  Thomas M. Trent ,  Kevin G. Duesman ,  James E. O'Toole

    发明人： Wen-Foo Chern ,  Ward M. Parkinson ,  Thomas M. Trent ,  Kevin G. Duesman ,  James E. O'Toole

    IPC分类号： H01L27/02 ,  H01L27/08 ,  H05K1/02

    CPC分类号： H01L27/0805 ,  H01L27/0214 ,  H05K1/0231

    摘要： An integrated cirucuit is provided with a depletion mode filter capacitor, which reduces voltage spiking, while at the same time avoiding latchup problems caused by the capacitor. The depletion mode capacitor has a barrier layer which is doped to an opposite conductivity type as the integrated circuit's substrate, achieved by doping to provide an opposite difference from four valence electrons as the substrate. The barrier is formed as a part of a CMOS process, in a manner which avoids additional process steps. The capacitor is formed with one node connected to ground or substrate, and the other node directly to a power bus. The capacitor is located on open space available on the whole siliocn chip (memory as well as logic chip), particularly directly underneath the metal power bus to achieve an on-chip power bus decoupling capacitor wth capacitance in excess of 0.001 .mu.F.

    摘要翻译： 一个集成的cirucuit配备有耗尽型滤波电容，可以减少电压尖峰，同时避免电容引起的闭锁问题。 耗尽型电容器具有阻挡层，其被掺杂成与集成电路的衬底相反的导电类型，通过掺杂实现，以提供与四价电子相反的差异作为衬底。 阻挡层以避免额外工艺步骤的方式形成为CMOS工艺的一部分。 电容器形成有一个节点连接到接地或基板，另一个节点直接连接到电源总线。 电容器位于整个硅芯片（存储器和逻辑芯片）上的开放空间上，特别是直接在金属电源总线下方，以实现片上电源总线去耦电容器超过0.001μF的电容。

    Semiconductor memory cell margin test circuit
    40.
    发明授权
    Semiconductor memory cell margin test circuit 失效
    半导体存储单元余量测试电路

    公开(公告)号：US4418403A

    公开(公告)日：1983-11-29

    申请号：US275057

    申请日：1981-02-02

    申请人： James E. O'Toole ,  Robert J. Proebsting

    发明人： James E. O'Toole ,  Robert J. Proebsting

    IPC分类号： G11C29/50 ,  G11C11/40

    CPC分类号： G11C29/50

    摘要： A margin test circuit (10) is provided for a semiconductor memory circuit having a plurality of memory cells (16). Each of the memory cells (16) in one row of cells (16) are interconnected to a word line (14). The margin test circuit (10) further includes a row decoder/driver (12) which receives a variable voltage (V.sub.cc *) for changing the signal level stored within a memory cell (16) to thereby determine the marginal voltage level at which the memory cell (16) will maintain storage of a signal level. The variable voltage (V.sub.cc *) is the semiconductor memory circuit main supply source (V.sub.cc) in normal operation but can be forced to a different voltage during the margin test.

    摘要翻译： PCT No.PCT / US81 / 00136 Sec。 371日期1981年2月2日 102（e）1981年2月2日PCT提交1981年2月2日PCT公布。 公开号WO82 / 02792 日期为1982年8月19日。为具有多个存储单元（16）的半导体存储器电路提供裕度测试电路（10）。 一行单元（16）中的每个存储单元（16）互连到字线（14）。 边缘测试电路（10）还包括行解码器/驱动器（12），其接收用于改变存储在存储单元（16）内的信号电平的可变电压（Vcc *），从而确定存储器 单元（16）将保持信号电平的存储。 可变电压（Vcc *）是正常工作时的半导体存储器电路主电源（Vcc），但在裕度测试期间可以强制为不同的电压。