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72 条记录 (耗时 0.04 秒)

    Arithmetic circuit with multiplexed addend inputs
    31.
    发明授权
    Arithmetic circuit with multiplexed addend inputs 有权
    具有复用加法输入的算术电路

    公开(公告)号：US07480690B2

    公开(公告)日：2009-01-20

    申请号：US11019854

    申请日：2004-12-21

    申请人： James M. Simkins ,  Steven P. Young ,  Jennifer Wong ,  Bernard J. New ,  Alvin Y. Ching

    发明人： James M. Simkins ,  Steven P. Young ,  Jennifer Wong ,  Bernard J. New ,  Alvin Y. Ching

    IPC分类号： G06F7/48

    CPC分类号： G06F7/509

    摘要： Described are arithmetic circuits divided logically into a product generator and an adder. Multiplexing circuitry logically disposed between the product generator and the adder supports conventional functionality by providing partial products from the product generator to addend terminals of the adder. The multiplexing circuitry can also be controlled to direct a number of external added inputs to the adder. The additional addend inputs can include inputs and outputs cascaded from other arithmetic circuits.

    摘要翻译： 描述的是算术电路，逻辑上分为乘积发生器和加法器。 逻辑上位于产品发生器和加法器之间的多路复用电路通过提供来自产品发生器的部分乘积到加法器的末端来支持常规功能。 还可以控制复用电路以将多个外部添加的输入引导到加法器。 附加加数输入可以包括从其他算术电路级联的输入和输出。

    Mathematical circuit with dynamic rounding
    32.
    发明授权
    Mathematical circuit with dynamic rounding 有权
    具有动态四舍五入的数学电路

    公开(公告)号：US07467177B2

    公开(公告)日：2008-12-16

    申请号：US11019853

    申请日：2004-12-21

    申请人： James M. Simkins ,  Steven P. Young ,  Jennifer Wong ,  Bernard J. New ,  Alvin Y. Ching

    发明人： James M. Simkins ,  Steven P. Young ,  Jennifer Wong ,  Bernard J. New ,  Alvin Y. Ching

    IPC分类号： G06F7/38

    CPC分类号： G06F7/49963

    摘要： Described are mathematical circuits that perform flexible rounding schemes. The circuits require few additional resources and can be adjusted dynamically to change the number of bits involved in the rounding. In one embodiment, a DSP circuit stores a rounding constant selected from the group of binary numbers 2(M−1) and 2(M−1)−1, calculates a correction factor, and sums the rounding constant, the correction factor, and a data item to obtain a rounded data item.

    摘要翻译： 描述了执行灵活舍入方案的数学电路。 这些电路需要很少的额外资源，并且可以动态调整以改变舍入所涉及的位数。 在一个实施例中，DSP电路存储从二进制数2（M-1）和2（M-1）-1组中选择的舍入常数，计算校正因子，并将舍入常数，校正因子和 一个数据项以获得舍入的数据项。

    Digital clock manager having cascade voltage switch logic clock paths
    33.
    发明授权
    Digital clock manager having cascade voltage switch logic clock paths 有权
    数字时钟管理器具有级联电压开关逻辑时钟路径

    公开(公告)号：US07038519B1

    公开(公告)日：2006-05-02

    申请号：US10837324

    申请日：2004-04-30

    申请人： Raymond C. Pang ,  Jennifer Wong

    发明人： Raymond C. Pang ,  Jennifer Wong

    IPC分类号： H03H11/26

    CPC分类号： H03K19/1738 ,  H03H11/26 ,  H03K2005/00195 ,  H03K2005/00228 ,  H03K2005/00234

    摘要： A digital clock manager having differential clock signal paths is provided. The differential clock signal paths are provided by replacing single-ended circuit elements of a conventional digital clock manager with symmetrical cascade voltage switch logic (CVSL) circuit elements, including CVSL delay buffers, CVSL multiplexers, CVSL AND gates, CVSL OR gates and CVSL set-reset latches. These symmetrical CVSL AND gates, CVSL OR gates and CVSL set-reset latches represent new circuit elements.

    摘要翻译： 提供具有差分时钟信号路径的数字时钟管理器。 差分时钟信号路径通过用传统数字时钟管理器的单端电路元件替代对称级联电压开关逻辑（CVSL）电路元件来提供，包括CVSL延迟缓冲器，CVSL多路复用器，CVSL与门，CVSL或门和CVSL组 - 锁存器。 这些对称的CVSL与门，CVSL或门和CVSL设置复位锁存器代表新的电路元件。

    Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocks
    34.
    发明授权
    Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocks 有权
    在逻辑块阵列中提供紧密耦合的处理器和RAM块列的结构和方法

    公开(公告)号：US06803786B1

    公开(公告)日：2004-10-12

    申请号：US10386955

    申请日：2003-03-11

    申请人： Goran Bilski ,  Ralph D. Wittig ,  Jennifer Wong ,  David B. Squires

    发明人： Goran Bilski ,  Ralph D. Wittig ,  Jennifer Wong ,  David B. Squires

    IPC分类号： H03K19177

    CPC分类号： H03K19/1776 ,  G06F15/7867 ,  H03K19/17732 ,  H03K19/17736 ,  H03K19/17796

    摘要： Structures and methods of including processor capabilities in an existing PLD architecture with minimal disruption to the existing general interconnect structure. In a PLD including a column of block RAM (BRAM) blocks, the BRAM blocks are modified to create specialized logic blocks including a RAM, a processor, and a dedicated interface coupled between the RAM, the processor, and the general interconnect structure of the PLD. The additional area is obtained by increasing the width of the column of BRAM blocks. Because the interconnect structure remains virtually unchanged, the interconnections between the specialized logic blocks and the adjacent tiles are already in place, and the modifications do not affect the PLD routing software. In some embodiments, the processor can be optionally disabled, becoming transparent to the user. Other embodiments provide methods of modifying a PLD to include the structures and provide the capabilities described above.

    摘要翻译： 在现有PLD架构中包含处理器能力的结构和方法，对现有的一般互连结构的影响最小。 在包括块RAM（BRAM）块列的PLD中，BRAM块被修改以创建专用的逻辑块，包括RAM，处理器和耦合在RAM，处理器和通用互连结构之间的专用接口 PLD。 通过增加BRAM块的列的宽度来获得附加区域。 因为互连结构几乎保持不变，所以专用逻辑块和相邻的瓦片之间的互连已经就位，并且修改不影响PLD路由软件。 在一些实施例中，处理器可以可选地被禁用，对于用户变得透明。 其他实施例提供了修改PLD以包括结构并提供上述能力的方法。

    Programmable logic device including configuration data or user data memory slices
    36.
    发明授权
    Programmable logic device including configuration data or user data memory slices 失效

    公开(公告)号：US5784313A

    公开(公告)日：1998-07-21

    申请号：US516808

    申请日：1995-08-18

    申请人： Stephen M. Trimberger ,  Richard A. Carberry ,  Robert Anders Johnson ,  Jennifer Wong

    发明人： Stephen M. Trimberger ,  Richard A. Carberry ,  Robert Anders Johnson ,  Jennifer Wong

    IPC分类号： G06F17/50 ,  G11C5/00 ,  H03K19/177 ,  G11C13/00

    CPC分类号： H03K19/17776 ,  G06F17/5054 ,  H03K19/17752 ,  H03K19/17756 ,  H03K19/1776

    摘要： A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD comprises an interconnect structure and a plurality of programmable logic elements for configuring the interconnect structure. In either embodiment, at least one of the programmable logic elements includes N memory cells. A predetermined one of the N memory cells forms part of a memory slice, wherein at least a portion of each slice of the programmable logic device is allocated to either configuration data or user data memory. Typically, one memory slice provides one configuration of the programmable logic device. In accordance with one embodiment, a memory access port is coupled between at least one of the N memory cells and either one configurable element or the interconnect, thereby facilitating loading of new configuration data into other memory slices during the one configuration. The new configuration data may include off-chip or on-chip data. The present invention typically allocates at least one slice to user data memory and includes means for disabling access to at least one of the N memory cells.