公开(公告)号：US20120074501A1

公开(公告)日：2012-03-29

申请号：US12892465

申请日：2010-09-28

申请人： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin ,  Robert R. Robison

发明人： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin ,  Robert R. Robison

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/76879 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/092

摘要： Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), a PFET contact to a source/drain region of the PFET and an NFET contact to a source/drain region of the NFET. In a first embodiment, a silicon germanium (SiGe) layer is included only under the PFET contact, between the PFET contact and the source/drain region of the PFET. In a second embodiment, either the PFET contact extends into the source/drain region of the PFET or the NFET contact extends into the source/drain region of the NFET.

摘要翻译： 这里公开了使用触点在集成电路（IC）芯片中的器件上产生差分应力的各种方法和结构。 公开了具有p型场效应晶体管（PFET）和n型场效应晶体管（NFET）的IC芯片，与PFET的源极/漏极区域的PFET接触以及与源极/漏极区域的NFET接触 的NFET。 在第一实施例中，在PFET接触和PFET的源极/漏极区之间仅包含PFET接触下的硅锗（SiGe）层。 在第二实施例中，PFET触点延伸到PFET的源极/漏极区域中，或者NFET触点延伸到NFET的源极/漏极区域。

公开(公告)号：US08021950B1

公开(公告)日：2011-09-20

申请号：US12911940

申请日：2010-10-26

申请人： Wagdi W. Abadeer ,  Lilian Kamal, legal representative ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Tom C. Lee

发明人： Wagdi W. Abadeer ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Tom C. Lee

IPC分类号： H01L21/336

CPC分类号： H01L21/28044 ,  H01L21/268 ,  H01L29/1054 ,  H01L29/4925 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： Disclosed are embodiments of a semiconductor wafer processing method that allow device regions to be selectively annealed following back end of the line (BEOL) metal wiring formation without degrading wiring layer reliability. In the embodiments, a semiconductor device is formed adjacent to the top surface of a wafer such that it incorporates a selectively placed infrared absorbing layer (IAL). Then, following BEOL metal wiring formation, the bottom surface of the wafer is exposed to an infrared light having a wavelength that is transparent to the wafer. The infrared light is absorbed by and, thereby heats up the IAL to a first predetermined temperature (e.g., a dopant activation temperature, a temperature required for a state change, etc.). The resulting heat is transferred from the IAL to an adjacent region of the semiconductor device without raising the temperature of the metal wiring above a second predetermined temperature (e.g., a temperature that could degrade the metal wiring) that is lower than the first predetermined temperature.

摘要翻译： 公开了允许器件区域在线路后端（BEOL）金属布线形成之后选择性退火的半导体晶片处理方法的实施例，而不会降低布线层的可靠性。 在实施例中，半导体器件形成为与晶片的顶表面相邻，使得其结合有选择放置的红外线吸收层（IAL）。 然后，在BEOL金属布线形成之后，晶片的底面暴露于对晶片透明的波长的红外光。 红外光被IAL吸收，从而将IAL加热到第一预定温度（例如，掺杂剂活化温度，状态改变所需的温度等）。 所产生的热量从IAL转移到半导体器件的相邻区域，而不会将金属布线的温度升高到低于第一预定温度的第二预定温度（例如，可能降低金属布线的温度）。

公开(公告)号：US07935638B2

公开(公告)日：2011-05-03

申请号：US12566043

申请日：2009-09-24

申请人： James A. Culp ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin

发明人： James A. Culp ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/32139 ,  H01L21/0338 ,  H01L21/28123 ,  H01L21/3185

摘要： Methods and structures for enhancing the homogeneity in a ratio of perimeter to surface area among heterogeneous features in different substrate regions. At least one shape on the substrate includes an added edge effective to reduce a difference in the perimeter-to-surface area ratio between the features in a first substrate region and features in a second substrate region. The improved homogeneity in the perimeter-to-surface area ratio reduces variations in a thickness of a conformal layer deposited across the features in the first and second substrate regions.

摘要翻译： 用于增强不同基底区域中异质特征之间的周长与表面积之比的均匀性的方法和结构。 衬底上的至少一种形状包括有效减少第一衬底区域中的特征与第二衬底区域中的特征之间的周边表面积比的差异的附加边缘。 周边至表面积比的改善的均匀性降低了跨越第一和第二基底区域中的特征沉积的共形层的厚度变化。

公开(公告)号：US08780436B2

公开(公告)日：2014-07-15

申请号：US13343395

申请日：2012-01-04

申请人： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin

发明人： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin

IPC分类号： G02B26/00

CPC分类号： G02B26/0841 ,  G02B5/201

摘要： Direct view color displays and design structures of direct view color displays. The direct view displays include micromirrors having un-tilted and tilted states and multiple color filters or color reflectors.

摘要翻译： 直观视图彩色显示器和直观视图彩色显示器的设计结构。 直视图显示器包括具有不倾斜和倾斜状态的微镜，以及多个滤色器或彩色反射器。

公开(公告)号：US20130186754A1

公开(公告)日：2013-07-25

申请号：US13353523

申请日：2012-01-19

申请人： Kristin M. Ackerson ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Yen Li Lim

发明人： Kristin M. Ackerson ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Yen Li Lim

IPC分类号： G01N27/403 ,  G01N27/416 ,  H01L21/283

CPC分类号： G01N27/3276 ,  G01N27/22 ,  H01L23/5223 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/036 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05157 ,  H01L2224/0518 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05624 ,  H01L2224/13101 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4847 ,  H01L2224/48624 ,  H01L2224/48824 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

摘要： A biosensor capacitor, including a dielectric layer; a first metal layer in the dielectric layer; a passivation layer over the dielectric layer and the first metal layer; an isolation layer over the passivation layer; a probe DNA electrode connected to the first metal layer; a counter electrode connected to the first metal layer wherein the counter electrode forms an enclosure around the probe DNA electrode; and a bond pad connected to the first metal layer.

摘要翻译： 一种生物传感器电容器，包括介电层; 介电层中的第一金属层; 在所述介​​电层和所述第一金属层上的钝化层; 钝化层上的隔离层; 连接到第一金属层的探针DNA电极; 连接到所述第一金属层的对电极，其中所述对电极围绕所述探针DNA电极形成外壳; 以及连接到第一金属层的接合焊盘。

公开(公告)号：US08492807B2

公开(公告)日：2013-07-23

申请号：US12632040

申请日：2009-12-07

申请人： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin

发明人： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin

IPC分类号： H01L31/062

CPC分类号： G02B26/08 ,  B81B3/004 ,  B81B2201/047 ,  G02B7/023 ,  G02B26/0875

摘要： A tiltable micro-electro-mechanical (MEMS) system lens comprises a microscopic lens located on a front surface of a semiconductor-on-insulator (SOI) substrate and a semiconductor rim surrounding the periphery of the microscopic lens. Two horizontal semiconductor beams located at different heights are provided within a top semiconductor layer. The microscopic lens may be tilted by applying an electrical bias between the lens rim and one of the two semiconductor beams, thereby altering the path of an optical beam through the microscopic lens. An array of tiltable microscopic lenses may be employed to form a composite lens having a variable focal length may be formed. A design structure for such a tiltable MEMS lens is also provided.

摘要翻译： 可倾斜微电机械（MEMS）系统透镜包括位于绝缘体上半导体（SOI）衬底的前表面上的微观透镜和围绕微观透镜周边的半导体边缘。 位于不同高度的两个水平半导体光束设置在顶部半导体层内。 可以通过在透镜边缘和两个半导体束中的一个之间施加电偏压来倾斜微观透镜，从而改变光束通过微透镜的路径。 可以使用可倾斜微镜透镜的阵列来形成具有可变焦距的复合透镜。 还提供了这种可倾斜MEMS透镜的设计结构。

公开(公告)号：US08460981B2

公开(公告)日：2013-06-11

申请号：US12892465

申请日：2010-09-28

申请人： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin ,  Robert R. Robison

发明人： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin ,  Robert R. Robison

IPC分类号： H01L21/00

CPC分类号： H01L21/76879 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/092

摘要： Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), a PFET contact to a source/drain region of the PFET and an NFET contact to a source/drain region of the NFET. In a first embodiment, a silicon germanium (SiGe) layer is included only under the PFET contact, between the PFET contact and the source/drain region of the PFET. In a second embodiment, either the PFET contact extends into the source/drain region of the PFET or the NFET contact extends into the source/drain region of the NFET.

公开(公告)号：US08440519B2

公开(公告)日：2013-05-14

申请号：US12778319

申请日：2010-05-12

申请人： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin

发明人： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin

IPC分类号： H01L21/8238

CPC分类号： H01L29/66545 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7849

摘要： An improved semiconductor device manufactured using, for example, replacement gate technologies. The method includes forming a dummy gate structure having a gate stack and spacers. The method further includes forming a dielectric material adjacent to the dummy gate structure. The method further includes removing the spacers to form gaps, and implanting a halo extension through the gaps and into an underlying diffusion region.

公开(公告)号：US08334195B2

公开(公告)日：2012-12-18

申请号：US12556139

申请日：2009-09-09

申请人： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Daniel N. Maynard ,  Richard J. Rassel

发明人： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Daniel N. Maynard ,  Richard J. Rassel

IPC分类号： H01L21/22

CPC分类号： H01L27/14607 ,  H01L27/14689

摘要： CMOS pixel sensors with multiple pixel sizes and methods of manufacturing the CMOS pixel sensors with implant dose control are provided. The method includes forming a plurality of pixel sensors in a same substrate and forming a masking pattern over at least one of the plurality of pixel sensors that has a pixel size larger than a non-masked pixel sensor of the plurality of pixel sensors. The method further includes providing a single dosage implant to the plurality of pixel sensors. The at least one of the plurality of pixel sensors with the masking pattern receives a lower dosage than the non-masked pixel sensor.

摘要翻译： 提供具有多个像素尺寸的CMOS像素传感器和用植入剂量控制制造CMOS像素传感器的方法。 该方法包括在同一衬底中形成多个像素传感器，并在多个像素传感器中的至少一个像素尺寸上形成掩模图案，该像素传感器的像素尺寸大于多个像素传感器中的非掩蔽像素传感器。 该方法还包括向多个像素传感器提供单个剂量植入物。 具有掩蔽图案的多个像素传感器中的至少一个具有比非掩蔽像素传感器更低的剂量。

公开(公告)号：US08301290B2

公开(公告)日：2012-10-30

申请号：US12603679

申请日：2009-10-22

申请人： James A. Culp ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin

发明人： James A. Culp ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin

IPC分类号： G06F19/00

CPC分类号： G06F17/5068 ,  G06F2217/10

摘要： Disclosed are a system and a method of correcting systematic, design-based, parametric variations on integrated circuit chips to minimize circuit limited yield loss. Processing information and a map of a chip are stored. The processing information can indicate an impact, on a given device parameter, of changes in a value for a specification associated with a given process step. The map can indicate regional variations in the device parameter (e.g., threshold voltage). Based on the processing information and using the map as a guide, different values for the specification are determined, each to be applied in a different region of the integrated circuit chip during the process step in order to offset the mapped regional parametric variations. A process tool can then be selectively controlled to ensure that during chip manufacturing the process step is performed accordingly and, thereby to ensure that the regional parametric variations are minimized.

摘要翻译： 公开了一种用于校正集成电路芯片上的系统的，基于设计的参数变化的系统和方法，以最小化电路限制的产量损失。 存储处理信息和芯片的映射。 处理信息可以指示给定设备参数对与给定过程步骤相关联的规范的值的变化的影响。 地图可以指示设备参数中的区域变化（例如，阈值电压）。 基于处理信息并使用该图作为指导，确定规范的不同值，每个值在处理步骤期间应用于集成电路芯片的不同区域，以便抵消映射的区域参数变化。 然后可以选择性地控制处理工具，以确保在芯片制造期间相应地执行工艺步骤，从而确保区域参数变化最小化。