Patent search cpc:"H01L2224/036" Page 1

1.

发明公开
CONDUCTIVE BARRIER DIRECT HYBRID BONDING 审中-公开

公开(公告)号：US20240243085A1

公开(公告)日：2024-07-18

申请号：US18517681

申请日：2023-11-22

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Paul M. Enquist

IPC: H01L23/00 , H01L21/50 , H01L25/00 , H01L25/065

CPC classification number: H01L24/09 , H01L21/50 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/80 , H01L24/89 , H01L25/0657 , H01L25/50 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/036 , H01L2224/03616 , H01L2224/03825 , H01L2224/05005 , H01L2224/05007 , H01L2224/05026 , H01L2224/05078 , H01L2224/05082 , H01L2224/05124 , H01L2224/05147 , H01L2224/0556 , H01L2224/05561 , H01L2224/05562 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/05655 , H01L2224/05657 , H01L2224/05666 , H01L2224/05676 , H01L2224/05681 , H01L2224/05684 , H01L2224/05686 , H01L2224/08112 , H01L2224/08121 , H01L2224/08123 , H01L2224/08145 , H01L2224/08147 , H01L2224/80011 , H01L2224/80031 , H01L2224/80035 , H01L2224/80047 , H01L2224/80075 , H01L2224/80097 , H01L2224/80099 , H01L2224/8019 , H01L2224/80194 , H01L2224/80895 , H01L2224/80896 , H01L2224/80935 , H01L2224/80986 , H01L2225/06513

Abstract: A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region.

2.

发明授权
Conductive barrier direct hybrid bonding 有权

公开(公告)号：US11830838B2

公开(公告)日：2023-11-28

申请号：US17677161

申请日：2022-02-22

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Paul M. Enquist

IPC: H01L23/00 , H01L21/50 , H01L25/065 , H01L25/00

CPC classification number: H01L24/09 , H01L21/50 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/80 , H01L24/89 , H01L25/0657 , H01L25/50 , H01L2224/036 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/03616 , H01L2224/03825 , H01L2224/05005 , H01L2224/05007 , H01L2224/05026 , H01L2224/0556 , H01L2224/0557 , H01L2224/05078 , H01L2224/05082 , H01L2224/05124 , H01L2224/05147 , H01L2224/05562 , H01L2224/05573 , H01L2224/05655 , H01L2224/05657 , H01L2224/05666 , H01L2224/05676 , H01L2224/05681 , H01L2224/05684 , H01L2224/05686 , H01L2224/08112 , H01L2224/08121 , H01L2224/08123 , H01L2224/08145 , H01L2224/08147 , H01L2224/80011 , H01L2224/8019 , H01L2224/80031 , H01L2224/80035 , H01L2224/80047 , H01L2224/80075 , H01L2224/80097 , H01L2224/80099 , H01L2224/80194 , H01L2224/80895 , H01L2224/80896 , H01L2224/80935 , H01L2224/80986 , H01L2225/06513 , H01L2224/03462 , H01L2924/00014 , H01L2224/0345 , H01L2924/00014 , H01L2224/03452 , H01L2924/00014 , H01L2224/29339 , H01L2924/00014 , H01L2224/29386 , H01L2224/80895 , H01L2924/053 , H01L2224/80986 , H01L2224/80896 , H01L2224/05124 , H01L2924/00014 , H01L2224/05147 , H01L2924/00014 , H01L2224/05686 , H01L2924/04941 , H01L2224/05686 , H01L2924/04953 , H01L2224/05684 , H01L2924/049 , H01L2224/05676 , H01L2924/053 , H01L2224/05681 , H01L2924/01014 , H01L2924/049 , H01L2224/05666 , H01L2924/01014 , H01L2924/049 , H01L2224/05684 , H01L2924/01005 , H01L2924/049 , H01L2224/05655 , H01L2924/051 , H01L2924/00014 , H01L2224/05657 , H01L2924/01074 , H01L2224/05657 , H01L2924/01074 , H01L2924/042

Abstract: A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region.

3.

发明授权
Conductive barrier direct hybrid bonding 有权

公开(公告)号：US09953941B2

公开(公告)日：2018-04-24

申请号：US14835379

申请日：2015-08-25

Applicant: INVENSAS BONDING TECHNOLOGIES, INC.

Inventor： Paul M. Enquist

IPC: H01L23/00 , H01L25/065 , H01L25/00 , H01L21/50

CPC classification number: H01L24/09 , H01L21/50 , H01L24/03 , H01L24/80 , H01L24/89 , H01L25/0657 , H01L25/50 , H01L2224/036 , H01L2224/05005 , H01L2224/05078 , H01L2224/05082 , H01L2224/08145 , H01L2224/8019 , H01L2224/80895 , H01L2225/06513

Abstract: A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region.

4.

发明申请
SHEET MOLDING PROCESS FOR WAFER LEVEL PACKAGING 审中-公开

公开(公告)号：US20170372998A1

公开(公告)日：2017-12-28

申请号：US15194445

申请日：2016-06-27

Applicant: Yenhao Benjamin Chen

Inventor： Yenhao Benjamin Chen

IPC: H01L23/528 , H01L23/31 , H01L21/304 , H01L23/00 , H01L21/56

CPC classification number: H01L23/528 , H01L21/304 , H01L21/561 , H01L21/565 , H01L23/3114 , H01L23/3171 , H01L23/525 , H01L24/06 , H01L24/11 , H01L24/13 , H01L2224/02175 , H01L2224/02181 , H01L2224/0219 , H01L2224/022 , H01L2224/02206 , H01L2224/02215 , H01L2224/023 , H01L2224/03013 , H01L2224/03436 , H01L2224/036 , H01L2224/03602 , H01L2224/03828 , H01L2224/0384 , H01L2224/0391 , H01L2224/0401 , H01L2224/05124 , H01L2224/05147 , H01L2224/05569 , H01L2224/10145 , H01L2224/11013 , H01L2224/113 , H01L2224/11849 , H01L2224/13021 , H01L2224/13022 , H01L2224/13024 , H01L2224/81024

Abstract: Discussed generally herein are methods and devices including or providing a redistribution layer device without under ball metallization. A device can include a substrate, electrical interconnect circuitry in the substrate, redistribution layer (RDL) circuitry electrically connected to the electrical interconnect circuitry, a conductive bump electrically connected to the RDL circuitry, the conductive bump interfacing directly with the RDL circuitry, and a sheet molding material over the substrate.

5.

发明申请
EMBEDDING THIN CHIPS IN POLYMER 审中-公开

公开(公告)号：US20170200670A1

公开(公告)日：2017-07-13

申请号：US15412993

申请日：2017-01-23

Applicant: MC10, Inc.

Inventor： Conor Rafferty , Mitul Dalal

IPC: H01L23/498 , H01L23/00 , H01L21/56 , H01L23/538 , H01L23/31 , H01L21/683

CPC classification number: H01L23/4985 , H01L21/56 , H01L21/6836 , H01L23/16 , H01L23/3107 , H01L23/3121 , H01L23/49822 , H01L23/49827 , H01L23/5389 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/29 , H01L24/82 , H01L2221/68327 , H01L2221/68381 , H01L2224/02379 , H01L2224/03436 , H01L2224/036 , H01L2224/0401 , H01L2224/04105 , H01L2224/05144 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05184 , H01L2224/05548 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2224/8203 , H01L2224/82039 , H01L2224/83132 , H01L2224/83192 , H01L2224/92244 , H01L2924/07802 , H01L2924/12042 , H01L2924/12043 , H01L2924/15153 , H05K1/0283 , H05K1/185 , H05K1/189 , H05K2203/1469 , H01L2924/00 , H01L2924/00014

Abstract: Systems and methods are provided for the embedding of thin chips. A well region is generated in a substrate that includes a conductive material disposed on a flexible polymer. The standoff well region can be generated by pattern the conductive material, where the thin chip is embedded in the standoff well region. A cavity can be generated in the polymer layer to form a polymer well region, where the thin chip is embedded in the polymer well region.

6.

发明授权
Interconnect structures and methods of forming same 有权
Title translation: 互连结构及其形成方法

公开(公告)号：US09589862B2

公开(公告)日：2017-03-07

申请号：US13914426

申请日：2013-06-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsuan-Ting Kuo , Tsung-Yuan Yu , Hsien-Wei Chen , Wen-Hsiung Lu , Ming-Da Cheng , Chung-Shi Liu

IPC: H01L21/00 , H01L23/31 , H01L21/56 , H01L23/00

CPC classification number: H01L23/3171 , H01L21/563 , H01L21/566 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/0345 , H01L2224/03452 , H01L2224/0347 , H01L2224/036 , H01L2224/03828 , H01L2224/0401 , H01L2224/05548 , H01L2224/05568 , H01L2224/05573 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05684 , H01L2224/10126 , H01L2224/11334 , H01L2224/1145 , H01L2224/11462 , H01L2224/1181 , H01L2224/11849 , H01L2224/119 , H01L2224/1191 , H01L2224/13022 , H01L2224/13082 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2224/81024 , H01L2224/81191 , H01L2224/81815 , H01L2224/83104 , H01L2224/83855 , H01L2924/00014 , H01L2924/01046 , H01L2924/01079 , H01L2924/014

Abstract: Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is a method of forming an interconnect structure, the method including forming a first post-passivation interconnect (PPI) over a first substrate, forming a second PPI over the first substrate, and forming a first conductive connector on the first PPI. The method further includes forming a second conductive connector on the second PPI, and forming a molding compound on top surfaces of the first and second PPIs and surrounding portions of the first and second connectors, a first section of molding compound being laterally between the first and second connectors, the first section of molding compound having a curved top surface.

Abstract translation: 本公开的实施例包括互连结构和形成互连结构的方法。实施例是形成互连结构的方法，该方法包括在第一衬底上形成第一钝化后互连（PPI），在第一衬底上形成第二PPI，以及在第一PPI上形成第一导电连接器。该方法还包括在第二PPI上形成第二导电连接器，以及在第一和第二PPI的顶表面和第一和第二连接器的周围部分上形成模制化合物，模制化合物的第一部分横向在第一和第二PPI之间第二连接器，第一部分模塑料具有弯曲的顶表面。

7.

发明授权
Semiconductor devices having metal bumps with flange 有权
Title translation: 半导体器件具有带凸缘的金属凸块

公开(公告)号：US09564410B2

公开(公告)日：2017-02-07

申请号：US14793813

申请日：2015-07-08

Applicant: Texas Instruments Incorporated

Inventor： Floro Lopez Camenforte, III , James Raymond Maliclic Baello , Armando Tresvalles Clarina, Jr.

IPC: H01L21/50 , H01L21/48 , H01L23/498 , H01L23/00 , H01L21/768 , H01L21/78

CPC classification number: H01L24/13 , H01L21/4853 , H01L21/76834 , H01L21/78 , H01L23/49844 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/94 , H01L2224/0345 , H01L2224/0346 , H01L2224/036 , H01L2224/0401 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05541 , H01L2224/05572 , H01L2224/05582 , H01L2224/05647 , H01L2224/0569 , H01L2224/1145 , H01L2224/1146 , H01L2224/116 , H01L2224/13005 , H01L2224/13007 , H01L2224/13016 , H01L2224/13144 , H01L2224/13147 , H01L2224/16227 , H01L2224/16245 , H01L2224/81191 , H01L2224/814 , H01L2224/94 , H01L2924/01022 , H01L2924/01042 , H01L2924/01073 , H01L2924/01074 , H01L2924/2064 , H01L2924/3512 , H01L2924/00014 , H01L2924/013 , H01L2924/014 , H01L2224/11 , H01L2224/03 , H01L2924/207

Abstract: A semiconductor device having a terminal site (100) including a flat pad (110) of a first metal covered by a layer (130) of dielectric material, the layer over the pad parallel to the pad and having a window of a first diameter (132) exposing the surface of the underlying pad. The terminal site further has a patch-shaped film (140) of a second metal covering the surface of the exposed first metal and the surface of an annulus of the dielectric layer framing the window, the film patch having a second diameter (141) greater than the first diameter; and a bump (150) of a third metal adhering to the film, the bump having a third diameter (151) smaller than the second diameter, whereby the film protrudes like a flange from the bump.

Abstract translation: 一种半导体器件，具有端子部位（100），该端子部位（100）包括由电介质材料层（130）覆盖的第一金属的平坦焊盘（110），所述焊盘上方的层平行于焊盘并具有第一直径的窗口 132）暴露下面的垫的表面。终端位置还具有覆盖暴露的第一金属的表面的第二金属的片状膜（140）和构成窗口的电介质层的环的表面，膜片具有更大的第二直径（141）比第一个直径; 以及附着在所述膜上的第三金属的凸块（150），所述凸块具有比所述第二直径小的第三直径（151），由此所述膜从所述凸块凸出成凸缘。

8.

发明申请
PACKAGING STRUCTURE 有权
Title translation: 包装结构

公开(公告)号：US20170033071A1

公开(公告)日：2017-02-02

申请号：US15202700

申请日：2016-07-06

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Sumihiro ICHIKAWA

IPC: H01L23/00 , H01L23/498 , H01L23/29 , H01L25/065 , H01L23/31

CPC classification number: H01L24/17 , H01L23/295 , H01L23/3142 , H01L23/49811 , H01L23/49833 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2224/036 , H01L2224/0401 , H01L2224/111 , H01L2224/1132 , H01L2224/11334 , H01L2224/1147 , H01L2224/1184 , H01L2224/11845 , H01L2224/11848 , H01L2224/119 , H01L2224/13005 , H01L2224/13014 , H01L2224/13109 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2224/1319 , H01L2224/1403 , H01L2224/14051 , H01L2224/14131 , H01L2224/14136 , H01L2224/14179 , H01L2224/14505 , H01L2224/16145 , H01L2224/16148 , H01L2224/16227 , H01L2224/16238 , H01L2224/2929 , H01L2224/29387 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/81065 , H01L2224/81143 , H01L2224/81193 , H01L2224/81856 , H01L2224/81862 , H01L2224/81895 , H01L2224/81907 , H01L2224/81986 , H01L2224/83104 , H01L2224/83862 , H01L2224/92125 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06565 , H01L2225/06593 , H01L2924/00015 , H01L2924/14 , H05K3/305 , H05K3/328 , H05K3/368 , H01L2224/81121 , H01L2224/81 , H01L2924/00014 , H01L2924/0665 , H01L2924/05442 , H01L2224/034 , H01L2224/113 , H01L2924/00012 , H01L2224/81203 , H01L2924/00

Abstract: A packaging structure includes a first substrate including a first metal terminal and a first protruding resin portion formed at a first surface; a second substrate including a second metal terminal and a second protruding resin portion formed at a second surface, the second metal terminal being made of the same kind of metal as the first metal terminal; and a sealing portion filled between the first surface of the first substrate and the second surface of the second substrate, the first metal terminal and the second metal terminal being directly bonded with each other, the first protruding resin portion and the second protruding resin portion being directly bonded with each other, each of the first protruding resin portion and the second protruding resin portion being made of a resin material that does not include fillers, and the sealing portion being made of a resin material including fillers.

Abstract translation: 包装结构包括：第一基板，包括形成在第一表面的第一金属端子和第一突出树脂部分; 第二基板，包括形成在第二表面的第二金属端子和第二突出树脂部分，所述第二金属端子由与所述第一金属端子相同种类的金属制成; 以及填充在第一基板的第一表面和第二基板的第二表面之间的密封部分，第一金属端子和第二金属端子彼此直接接合，第一突出树脂部分和第二突出树脂部分是彼此直接接合，第一突出树脂部分和第二突出树脂部分由不包括填料的树脂材料制成，并且密封部分由包括填料的树脂材料制成。