公开(公告)号：US07829879B2

公开(公告)日：2010-11-09

申请号：US12033519

申请日：2008-02-19

申请人： Rolf Weis ,  Thomas Happ

发明人： Rolf Weis ,  Thomas Happ

IPC分类号： H01L29/02

CPC分类号： H01L27/2409 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/148

摘要： An integrated circuit includes a first contact, a second contact, and a U-shaped access device coupled to the first contact and the second contact. The integrated circuit includes self-aligned dielectric material isolating the first contact from the second contact.

摘要翻译： 集成电路包括耦合到第一触点和第二触点的第一触点，第二触点和U形存取装置。 集成电路包括将第一接触与第二接触隔离的自对准电介质材料。

公开(公告)号：US07642586B2

公开(公告)日：2010-01-05

申请号：US11517634

申请日：2006-09-08

申请人： Rolf Weis

发明人： Rolf Weis

IPC分类号： H01L27/108

CPC分类号： H01L29/66621 ,  H01L27/10876 ,  H01L27/10882 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides an integrated memory cell array comprising: a semiconductor substrate; a plurality of cell transistor devices including: a pillar formed in said semiconductor substrate; a gate trench surrounding said pillar; a first source/drain region formed in an upper region of said pillar; a gate dielectric formed on the bottom of said gate trench and surrounding a lower region of said pillar; a gate formed on said gate dielectric in said gate trench and surrounding a lower region of said pillar; and a second source/drain region formed in an upper region of said semiconductor substrate adjoining said gate trench; a plurality of bitlines being connected to respective first groups of first source/drain regions of said cell transistor devices; a plurality of wordlines connecting the respective gates of second groups said cell transistor devices; and a plurality of cell capacitor devices being connected to the second source/drain regions of said cell transistor devices.

摘要翻译： 本发明提供一种集成存储单元阵列，包括：半导体衬底; 多个单元晶体管器件，包括：形成在所述半导体衬底中的柱; 围绕所述支柱的栅极沟槽; 形成在所述柱的上部区域中的第一源极/漏极区域; 形成在所述栅极沟槽的底部并围绕所述柱的下部区域的栅极电介质; 形成在所述栅极沟槽中的所述栅极电介质上并围绕所述柱的下部区域的栅极; 以及形成在与所述栅极沟槽相邻的所述半导体衬底的上部区域中的第二源极/漏极区域; 多个位线连接到所述单元晶体管器件的第一源/漏区的相应第一组; 连接第二组的各个栅极的多个字线，所述单元晶体管器件; 并且多个单元电容器器件连接到所述单元晶体管器件的第二源极/漏极区域。

公开(公告)号：US20090127608A1

公开(公告)日：2009-05-21

申请号：US11943482

申请日：2007-11-20

申请人： Rolf Weis

发明人： Rolf Weis

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L27/0207 ,  G11C5/063 ,  G11C11/4097 ,  H01L27/10817 ,  H01L27/10855 ,  H01L27/10882 ,  H01L27/10888

摘要： An integrated circuit including a memory cell array is shown. The memory cell array comprises word lines extending in a first direction and bit lines extending in a second direction intersecting the first direction and memory cells. The memory cells may include storage elements, bit line contacts for coupling a corresponding memory cell to a corresponding bit line. The bit line contacts are arranged in a checkerboard pattern with respect to the first direction, and the storage elements are arranged in a regular grid along the first and second directions, respectively.

摘要翻译： 示出了包括存储单元阵列的集成电路。 存储单元阵列包括沿第一方向延伸的字线和沿与第一方向相交的第二方向延伸的位线和存储单元。 存储器单元可以包括存储元件，用于将相应的存储器单元耦合到对应的位线的位线触点。 位线触点相对于第一方向布置成棋盘图案，并且存储元件分别沿着第一和第二方向排列成规则的格栅。

公开(公告)号：US20080044980A1

公开(公告)日：2008-02-21

申请号：US11507647

申请日：2006-08-21

申请人： Kimberly Wilson ,  Hans-Peter Moll ,  Rolf Weis ,  Phillip Stopford ,  Frank Ludwig

发明人： Kimberly Wilson ,  Hans-Peter Moll ,  Rolf Weis ,  Phillip Stopford ,  Frank Ludwig

IPC分类号： H01L21/76

CPC分类号： H01L21/76224 ,  Y10S438/942 ,  Y10S438/952

摘要： A method of forming a semiconductor device includes depositing a fill material (4) on a substrate portion (2) and on a dielectric layer (3) being disposed on the substrate (1) and having an opening (10) located above the substrate portion (2), removing the fill material (4) disposed above the dielectric layer (3), thereby leaving an exposed top surface (6) of the dielectric layer (3) and residual fill material (15) within the opening (10), forming a hard mask material (5) on the exposed top surface (6) of the dielectric layer (3) and on the residual fill material (15), patterning the hard mask material (5) for forming a hard mask (25) having trenches (8a, 8b) extending along a lateral direction (X) and exposing portions of the residual fill material (15) adjacent to the dielectric layer (3) and portions of the dielectric layer (3) adjacent to the residual fill material (15), anisotropically etching the dielectric layer (3), the residual fill material (15) and the substrate (1) selectively to the hard mask (5), thereby forming at least a first and a second isolation trench (11a, 11b) extending along the lateral direction (X).

摘要翻译： 一种形成半导体器件的方法包括在衬底部分（2）上沉积填充材料（4）和设置在衬底（1）上并具有位于衬底部分上方的开口（10）的介电层（3） （2），去除设置在电介质层（3）上方的填充材料（4），从而在开口（10）内留下介电层（3）的暴露的顶表面（6）和残余填充材料（15） 在所述介​​电层（3）的暴露的顶表面（6）和所述残留填充材料（15）上形成硬掩模材料（5），对所述硬掩模材料（5）进行图案化以形成硬掩模（25），所述硬掩模材料（25） 沿着横向方向（X）延伸的沟槽（8a，8b）和暴露邻近电介质层（3）的残余填充材料（15）的部分和与残余填充材料相邻的介电层（3）的部分 （15），各向异性地蚀刻介电层（3），残留 填充材料（15）和基板（1）选择性地连接到硬掩模（5），从而形成沿着横向（X）延伸的至少第一和第二隔离沟槽（11a，11b）。

公开(公告)号：US07244980B2

公开(公告)日：2007-07-17

申请号：US10774827

申请日：2004-02-09

申请人： Rolf Weis ,  Ramachandra Divakaruni ,  Larry Nesbit

发明人： Rolf Weis ,  Ramachandra Divakaruni ,  Larry Nesbit

IPC分类号： H01L29/94

CPC分类号： H01L27/10867 ,  H01L27/10864

摘要： A memory cell is formed for a memory cell array that is comprised of a plurality of the memory cells arranged in rows and columns. Deep trenches having sidewalls is formed within a semiconductor substrate. A buried plate region adjoining a deep trench is formed within the semiconductor substrate, and a dielectric film is formed along the sidewalls of the deep trench. A masking layer is patterned such that a portion of the dielectric film is covered by the masking layer and a remaining portion of the dielectric film is exposed. An upper region of the exposed portion of the dielectric film is removed such that a trench collar is formed along a middle portion of a side of the deep trench. The deep trench is partly filled with doped polysilicon. The dopants in the polysilicon diffuse through the side of the deep trench into adjoining regions of the semiconductor substrate during subsequent thermal processing steps to form a buried strap region along a side of the deep trench. The semiconductor substrate is patterned and etched to form at least one isolation trench that adjoins the isolation trench and two of the deep trenches and includes a buried strap region. The patterning uses a mask comprised of a lines and spaces pattern such that at least one active area is defined by the isolation trench and by the deep trench. Each of the lines and the spaces extends across the memory cell array.

摘要翻译： 为存储单元阵列形成存储单元，存储单元阵列由以行和列排列的多个存储单元组成。 具有侧壁的深沟槽形成在半导体衬底内。 在半导体衬底内形成与深沟槽相邻的掩埋板区域，沿着深沟槽的侧壁形成电介质膜。 图案化掩模层，使得电介质膜的一部分被掩蔽层覆盖，并且电介质膜的剩余部分被暴露。 去除电介质膜的暴露部分的上部区域，使得沿着深沟槽的一侧的中间部分形成沟槽套环。 深沟槽部分填充有掺杂多晶硅。 在随后的热处理步骤期间，多晶硅中的掺杂剂通过深沟槽的侧面扩散到半导体衬底的相邻区域中，以沿着深沟槽的一侧形成掩埋带区域。 对半导体衬底进行图案化和蚀刻以形成邻接隔离沟槽和两个深沟槽中的至少一个隔离沟槽并且包括掩埋带区域。 图案化使用由线和空间图案组成的掩模，使得至少一个有源区域由隔离沟槽和深沟槽限定。 每个行和空格都延伸穿过存储单元阵列。

公开(公告)号：US20060267158A1

公开(公告)日：2006-11-30

申请号：US11431808

申请日：2006-05-10

申请人： Rolf Weis

发明人： Rolf Weis

IPC分类号： H01L23/552

CPC分类号： G11C11/4097 ,  G11C7/18 ,  H01L27/10885

摘要： A semiconductor memory apparatus having bit lines for driving a selection transistor with a storage capacitor is disclosed. In one embodiment, shielding between adjacent bit lines by means of a conductive shielding device results in a reduction in the bit line-bit line coupling and makes it possible to improve the charge retention time even when avoiding concepts which use chip area such as a bit line twist.

摘要翻译： 公开了一种具有用于驱动具有存储电容器的选择晶体管的位线的半导体存储装置。 在一个实施例中，通过导电屏蔽装置在相邻位线之间的屏蔽导致位线位线耦合的减少，并且使得即使避免使用诸如位的芯片区域的概念也可以改善电荷保留时间 线扭。

公开(公告)号：US20060160300A1

公开(公告)日：2006-07-20

申请号：US11039740

申请日：2005-01-20

申请人： Rolf Weis

发明人： Rolf Weis

IPC分类号： H01L21/8242

CPC分类号： H01L27/10894 ,  H01L21/76802 ,  H01L21/76885 ,  H01L21/76895 ,  H01L27/10852 ,  H01L28/91

摘要： A storage capacitor suitable for use in a DRAM cell, as well as to a method of manufacturing such a storage capacitor is disclosed. The storage capacitor is formed at least partially above a semiconductor substrate surface. The invention also includes a memory array employing the storage capacitor.

摘要翻译： 公开了适用于DRAM单元的存储电容器以及制造这种存储电容器的方法。 存储电容器至少部分地形成在半导体衬底表面上方。 本发明还包括采用存储电容器的存储器阵列。

公开(公告)号：US20060054958A1

公开(公告)日：2006-03-16

申请号：US11220920

申请日：2005-09-08

申请人： Rolf Weis ,  Ulrike Gruening Von Schwerin

发明人： Rolf Weis ,  Ulrike Gruening Von Schwerin

IPC分类号： H01L29/94

CPC分类号： H01L27/10891 ,  H01L27/10861 ,  H01L29/785

摘要： A DRAM memory cell array is fabricated such that, for each memory cell of the array, the gate electrode is initially produced such that it is insulated from all the other gate electrodes assigned to a certain word line, and is only connected to the other gate electrodes assigned to the corresponding word line via the word line in a subsequent step.

公开(公告)号：US06806200B2

公开(公告)日：2004-10-19

申请号：US10291951

申请日：2002-11-08

申请人： David Dobuzinsky ,  Siddhartha Panda ,  Rolf Weis ,  Richard Wise

发明人： David Dobuzinsky ,  Siddhartha Panda ,  Rolf Weis ,  Richard Wise

IPC分类号： H01L21302

CPC分类号： H01L21/3065

摘要： A method is disclosed for improving etch uniformity in deep silicon etching of a monocrystalline silicon wafer. Such method includes forming a pad dielectric layer on a wafer including monocrystalline silicon, forming a silicon layer over the pad dielectric layer, and then applying a clamp to an edge of the wafer. The silicon layer is then removed except in areas protected by the clamp. Thereafter, a hardmask layer is applied and patterned on the wafer; and the wafer is then directionally etched with the patterned hardmask to etch trenches in the monocrystalline silicon. In such manner, a source of silicon (in the silicon layer) is provided at the wafer edge, such that the silicon loading is improved. In addition, the silicon layer at the wafer edge forms a blocking layer which prevents formation of black silicon.

摘要翻译： 公开了一种用于改善单晶硅晶片的深硅蚀刻中的蚀刻均匀性的方法。 这种方法包括在包括单晶硅的晶片上形成焊盘电介质层，在焊盘介电层上形成硅层，然后在晶片的边缘上施加夹具。 然后除去在被夹具保护的区域之外除去硅层。 此后，将硬掩模层施加和图案化在晶片上; 然后用图案化的硬掩模对晶片进行定向蚀刻，以蚀刻单晶硅中的沟槽。以这种方式，在晶片边缘处提供硅源（在硅层中），使得硅负载得到改善。 此外，晶片边缘处的硅层形成防止形成黑色硅的阻挡层。

公开(公告)号：US06496401B2

公开(公告)日：2002-12-17

申请号：US09871011

申请日：2001-05-31

申请人： Rolf Weis

发明人： Rolf Weis

IPC分类号： G11C502

CPC分类号： H01L27/10841 ,  H01L27/0207 ,  H01L27/10885

摘要： A memory cell configuration has memory cells, each with a trench capacitor in a trench and a vertical transistor, which is used as a selection transistor. The trench capacitors in adjacent memory cells are arranged next to a bit line and are connected to the bit line via their selection transistor. Adjacent trench capacitors connected to a bit line are arranged alternately on the two sides of the bit line.

摘要翻译： 存储单元配置具有存储单元，每个单元具有沟槽中的沟槽电容器和用作选择晶体管的垂直晶体管。 相邻存储单元中的沟槽电容器被布置在位线旁边，并通过它们的选择晶体管连接到位线。 连接到位线的相邻沟槽电容器交替地布置在位线的两侧。