公开(公告)号：US08071442B2

公开(公告)日：2011-12-06

申请号：US12552642

申请日：2009-09-02

申请人： Stephan Kronholz ,  Markus Lenski ,  Andy Wei ,  Andreas Ott

发明人： Stephan Kronholz ,  Markus Lenski ,  Andy Wei ,  Andreas Ott

IPC分类号： H01L21/8242

CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7848

摘要： A strain-inducing semiconductor alloy may be formed on the basis of cavities which may have a non-rectangular shape, which may be maintained even during corresponding high temperature treatments by providing an appropriate protection layer, such as a silicon dioxide material. Consequently, a lateral offset of the strain-inducing semiconductor material may be reduced, while nevertheless providing a sufficient thickness of corresponding offset spacers during the cavity etch process, thereby preserving gate electrode integrity. For instance, P-channel transistors may have a silicon/germanium alloy with a hexagonal shape, thereby significantly enhancing the overall strain transfer efficiency.

摘要翻译： 应变诱导半导体合金可以基于可以具有非矩形形状的空腔形成，即使在相应的高温处理期间也可以通过提供适当的保护层（例如二氧化硅材料）来维持。 因此，可以减小应变诱导半导体材料的横向偏移，同时在腔蚀刻工艺期间提供足够厚度的相应的偏移间隔物，从而保持栅电极的完整性。 例如，P沟道晶体管可以具有六角形状的硅/锗合金，从而显着提高总的应变转移效率。

公开(公告)号：US06296889B1

公开(公告)日：2001-10-02

申请号：US09230677

申请日：1999-01-29

申请人： Andreas Ott ,  Alain Chaintreau ,  Laurent B. Fay

发明人： Andreas Ott ,  Alain Chaintreau ,  Laurent B. Fay

IPC分类号： A23L122

CPC分类号： C11B9/0015 ,  A23F5/465 ,  A23L27/2024

摘要： 1-nonen-3-one is added to food, pharamaceutical, cosmetic and perfume compositions to flavor the products and so that they impart aroma. It is added particularly to dairy products and coffee extract for enhancing the aroma imparted by those compositions. The 1-nonen-3-one may be combined with other compounds which provide flavor and aroma, and the combined compounds are added to the compositions.

摘要翻译： 将1-壬烯-3-酮加入到食品，药用品，化妆品和香料组合物中以使产品变味，从而赋予香味。 它特别添加到乳制品和咖啡提取物中，以增强由这些组合物赋予的香气。 1-壬烯-3-酮可以与提供风味和香气的其它化合物组合，并将组合的化合物加入到组合物中。

公开(公告)号：US08728896B2

公开(公告)日：2014-05-20

申请号：US13238180

申请日：2011-09-21

申请人： Stephan Kronholz ,  Andreas Ott ,  Ina Ostermay

发明人： Stephan Kronholz ,  Andreas Ott ,  Ina Ostermay

IPC分类号： H01L21/66 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L22/12

摘要： When forming sophisticated transistors requiring an embedded semiconductor alloy, the cavities may be formed with superior uniformity on the basis of, for instance, crystallographically anisotropic etch steps by providing a uniform oxide layer in order to reduce process related fluctuations or queue time variations. The uniform oxide layer may be formed on the basis of an APC control regime.

摘要翻译： 当形成需要嵌入式半导体合金的复杂晶体管时，可以通过提供均匀的氧化物层来在例如晶体学各向异性蚀刻步骤的基础上形成具有优异均匀性的空腔，以便减少与工艺相关的波动或排队时间变化。 可以基于APC控制方式形成均匀的氧化物层。

公开(公告)号：US08703551B2

公开(公告)日：2014-04-22

申请号：US13102680

申请日：2011-05-06

申请人： Stephan Kronholz ,  Andreas Ott

发明人： Stephan Kronholz ,  Andreas Ott

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/8228 ,  H01L21/8238 ,  H01L21/20 ,  H01L21/36 ,  H01L21/302

CPC分类号： H01L21/30608 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/84

摘要： Disclosed herein is a method of forming a semiconductor device. In one example, the method comprises performing at least one etching process to reduce a thickness of a P-active region of a semiconducting substrate to thereby define a recessed P-active region, performing a process in a process chamber to selectively form an as-deposited layer of a semiconductor material on the recessed P-active region, wherein the step of performing the at least one etching process is performed outside of the process chamber, and performing an etching process in the process chamber to reduce a thickness of the as-deposited layer of semiconductor material.

摘要翻译： 本文公开了形成半导体器件的方法。 在一个示例中，该方法包括执行至少一个蚀刻工艺以减小半导体衬底的P活性区域的厚度，从而限定凹陷的P活性区域，在处理室中执行选择性地形成 在凹陷的P活性区域上形成半导体材料的沉积层，其中执行所述至少一个蚀刻工艺的步骤在所述处理室的外部进行，并且在所述处理室中进行蚀刻处理以减小所述至少一个蚀刻工艺的厚度， 半导体材料的沉积层。

公开(公告)号：US20120153402A1

公开(公告)日：2012-06-21

申请号：US13238180

申请日：2011-09-21

申请人： Stephan Kronholz ,  Andreas Ott ,  Ina Ostermay

发明人： Stephan Kronholz ,  Andreas Ott ,  Ina Ostermay

IPC分类号： H01L27/088 ,  H01L21/66

CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L22/12

摘要： When forming sophisticated transistors requiring an embedded semiconductor alloy, the cavities may be formed with superior uniformity on the basis of, for instance, crystallographically anisotropic etch steps by providing a uniform oxide layer in order to reduce process related fluctuations or queue time variations. The uniform oxide layer may be formed on the basis of an APC control regime.

摘要翻译： 当形成需要嵌入式半导体合金的复杂晶体管时，可以通过提供均匀的氧化物层来在例如晶体学各向异性蚀刻步骤的基础上形成具有优异均匀性的空腔，以便减少与工艺相关的波动或排队时间变化。 可以基于APC控制方式形成均匀的氧化物层。

公开(公告)号：US20110073963A1

公开(公告)日：2011-03-31

申请号：US12893051

申请日：2010-09-29

申请人： Sven Beyer ,  Klaus Hempel ,  Andreas Ott ,  Stephan Kruegel

发明人： Sven Beyer ,  Klaus Hempel ,  Andreas Ott ,  Stephan Kruegel

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L29/6653 ,  H01L29/517 ,  H01L29/66545

摘要： In a replacement gate approach, a superior cross-sectional shape of the gate opening may be achieved by performing a material erosion process in an intermediate state of removing the placeholder material. Consequently, the remaining portion of the placeholder material may efficiently protect the underlying sensitive materials, such as a high-k dielectric material, when performing the corner rounding process sequence.

摘要翻译： 在替代浇口方法中，可以通过在去除占位材料的中间状态下进行材料侵蚀过程来实现闸门开口的优越的横截面形状。 因此，当执行拐角舍入处理顺序时，占位符材料的剩余部分可以有效地保护诸如高k电介质材料的底层敏感材料。

公开(公告)号：US20100164014A1

公开(公告)日：2010-07-01

申请号：US12637112

申请日：2009-12-14

申请人： Stephan Kronholz ,  Andreas Ott

发明人： Stephan Kronholz ,  Andreas Ott

IPC分类号： H01L27/088 ,  H01L21/336 ,  H01L21/8236

CPC分类号： H01L21/823412 ,  H01L21/82345 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/84

摘要： A threshold adjusting semiconductor material, such as a silicon/germanium alloy, may be provided selectively for one type of transistors on the basis of enhanced deposition uniformity. For this purpose, the semiconductor alloy may be deposited on the active regions of any transistors and may subsequently be patterned on the basis of a highly controllable patterning regime. Consequently, threshold variability may be reduced.

摘要翻译： 基于增强的沉积均匀性，可以选择性地为一种类型的晶体管提供阈值调节半导体材料，例如硅/锗合金。 为此，可以将半导体合金沉积在任何晶体管的有源区上，并且随后可以基于高度可控的图案化状态来图案化。 因此，阈值变化可能降低。

公开(公告)号：US20100078689A1

公开(公告)日：2010-04-01

申请号：US12552642

申请日：2009-09-02

申请人： Stephan Kronholz ,  Markus Lenski ,  Andy Wei ,  Andreas Ott

发明人： Stephan Kronholz ,  Markus Lenski ,  Andy Wei ,  Andreas Ott

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7848

摘要： A strain-inducing semiconductor alloy may be formed on the basis of cavities which may have a non-rectangular shape, which may be maintained even during corresponding high temperature treatments by providing an appropriate protection layer, such as a silicon dioxide material. Consequently, a lateral offset of the strain-inducing semiconductor material may be reduced, while nevertheless providing a sufficient thickness of corresponding offset spacers during the cavity etch process, thereby preserving gate electrode integrity. For instance, P-channel transistors may have a silicon/germanium alloy with a hexagonal shape, thereby significantly enhancing the overall strain transfer efficiency.

摘要翻译： 应变诱导半导体合金可以基于可以具有非矩形形状的空腔形成，即使在相应的高温处理期间也可以通过提供适当的保护层（例如二氧化硅材料）来维持。 因此，可以减小应变诱导半导体材料的横向偏移，同时在腔蚀刻工艺期间提供足够厚度的相应的偏移间隔物，从而保持栅电极的完整性。 例如，P沟道晶体管可以具有六角形状的硅/锗合金，从而显着提高总的应变转移效率。

公开(公告)号：US20130299874A1

公开(公告)日：2013-11-14

申请号：US13468777

申请日：2012-05-10

申请人： Joanna Wasyluk ,  Berthold Reimer ,  Carsten Reichel ,  Jamie Schaeffer ,  Yew Tuck Chow ,  Stephan Kronholz ,  Andreas Ott

发明人： Joanna Wasyluk ,  Berthold Reimer ,  Carsten Reichel ,  Jamie Schaeffer ,  Yew Tuck Chow ,  Stephan Kronholz ,  Andreas Ott

IPC分类号： H01L27/092 ,  H01L21/20

CPC分类号： H01L21/823807 ,  H01L21/02057 ,  H01L21/30608 ,  H01L21/823878

摘要： CMOS devices are enhanced by forming a recess in the positive channel for depositing SiGe. Embodiments include providing a positive channel region and a negative channel region in a silicon substrate for a CMOS device, with an STI region therebetween; removing a native oxide from above the positive channel region to expose a silicon substrate; forming a recess in the silicon substrate in the positive channel region adjacent the STI region; and depositing SiGe in the recess in the positive channel region, where an upper surface of the SiGe is substantially level with an upper surface of the negative channel region.

摘要翻译： 通过在正通道中形成用于沉积SiGe的凹槽来增强CMOS器件。 实施例包括在用于CMOS器件的硅衬底中提供正沟道区和负沟道区，其间具有STI区; 从正通道区域上方去除天然氧化物以暴露硅衬底; 在与STI区域相邻的正沟道区域中的硅衬底中形成凹部; 以及将SiGe沉积在正沟道区中的凹槽中，其中SiGe的上表面与负沟道区的上表面基本一致。

公开(公告)号：US20130115773A1

公开(公告)日：2013-05-09

申请号：US13289122

申请日：2011-11-04

申请人： Rohit Pal ,  Rolf Stephan ,  Andreas Ott

发明人： Rohit Pal ,  Rolf Stephan ,  Andreas Ott

IPC分类号： H01L21/311

CPC分类号： H01L21/3105 ,  H01L21/31155 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823437 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/84 ,  H01L29/66545 ,  H01L29/7833

摘要： When forming sophisticated high-k metal gate electrode structures on the basis of a replacement gate approach, pronounced loss of the interlayer dielectric material may be avoided by inserting at least one surface modification process, for instance in the form of a nitridation process. In this manner, leakage paths caused by metal residues formed in the interlayer dielectric material may be significantly reduced.

摘要翻译： 当基于替代栅极方法形成复杂的高k金属栅电极结构时，可以通过插入至少一个表面改性工艺（例如以氮化工艺的形式）来避免层间绝缘材料的显着损失。 以这种方式，可以显着地减少由层间电介质材料中形成的金属残留物引起的泄漏路径。