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    ITERATIVE WRITE PAUSING TECHNIQUES TO IMPROVE READ LATENCY OF MEMORY SYSTEMS
    31.
    发明申请
    ITERATIVE WRITE PAUSING TECHNIQUES TO IMPROVE READ LATENCY OF MEMORY SYSTEMS 有权
    迭代写暂停技术来改善读取存储器系统的延迟

    公开(公告)号：US20110026318A1

    公开(公告)日：2011-02-03

    申请号：US12533548

    申请日：2009-07-31

    申请人： Michele M. Franceschini ,  Luis A. Lastras-Montano ,  Moinuddin K. Qureshi ,  Vijayalakshmi Srinivasan

    发明人： Michele M. Franceschini ,  Luis A. Lastras-Montano ,  Moinuddin K. Qureshi ,  Vijayalakshmi Srinivasan

    IPC分类号： G11C11/00 ,  G11C7/00

    CPC分类号： G06F13/1642 ,  G06F13/161

    摘要： Iterative write pausing techniques to improve read latency of memory systems including memory systems with phase change memory (PCM) devices. A PCM device includes a plurality of memory locations and a mechanism for executing an iterative write to one or more of the memory locations in response to receiving a write command that includes data to be written. The executing includes initiating the iterative write, updating a state of the iterative write, pausing the iterative write including saving the state in response to receiving a pause command, and resuming the iterative write in response to receiving a resume command. The resuming is responsive to the saved state and to the data to be written.

    摘要翻译： 迭代写暂停技术，以提高内存系统（包括具有相变存储器（PCM）设备的存储器系统）的读取延迟。 PCM设备包括多个存储器位置和用于响应于接收到包括要写入的数据的写入命令而执行对一个或多个存储器位置的迭代写入的机制。 执行包括启动迭代写入，更新迭代写入的状态，暂停迭代写入，包括响应于接收到暂停命令而保存状态，以及响应于接收到恢复命令恢复迭代写入。 恢复响应于保存的状态和要写入的数据。

    Correction of structured burst errors in data
    33.
    发明授权
    Correction of structured burst errors in data 有权
    纠正数据中的结构突发错误

    公开(公告)号：US09071277B1

    公开(公告)日：2015-06-30

    申请号：US13556561

    申请日：2012-07-24

    申请人： Michele M. Franceschini ,  Luis A. Lastras-Montano

    发明人： Michele M. Franceschini ,  Luis A. Lastras-Montano

    IPC分类号： H03M13/29 ,  G06F11/10 ,  H03M13/15 ,  H04L1/00

    CPC分类号： H03M13/15 ,  H03M13/152 ,  H03M13/17 ,  H03M13/2906 ,  H04L1/0045

    摘要： Correction of structured burst errors in data is provided by a system that includes an encoder and is configured for performing a method. The method includes receiving data that includes a plurality of subsets of data. The data is encoded by an encoder using a combination of a first error correcting code and a second error correcting code. The first error correcting code is configured to provide error recovery from a structured burst error in one of the subsets of data, the structured burst error having a length less than a specified maximum length. The second error correcting code is configured to extend the first error correcting code to provide error recovery from the structured burst error in any of the subsets of data. The encoded data is output.

    摘要翻译： 数据中的结构化突发错误的校正由包括编码器并且被配置为执行方法的系统提供。 该方法包括接收包括多个数据子集的数据。 数据由编码器使用第一纠错码和第二纠错码的组合进行编码。 第一纠错码被配置为从数据子集之一中的结构化突发错误提供错误恢复，结构化突发错误的长度小于指定的最大长度。 第二纠错码被配置为扩展第一纠错码，以便在数据子集中的结构化突发错误中提供错误恢复。 输出编码数据。

    Reclaiming discarded solid state devices
    34.
    发明授权
    Reclaiming discarded solid state devices 有权
    回收废弃的固态设备

    公开(公告)号：US08868978B2

    公开(公告)日：2014-10-21

    申请号：US13396020

    申请日：2012-02-14

    申请人： Michele M. Franceschini ,  Ashish Jagmohan ,  Luis A. Lastras-Montano ,  Mayank Sharma

    发明人： Michele M. Franceschini ,  Ashish Jagmohan ,  Luis A. Lastras-Montano ,  Mayank Sharma

    IPC分类号： G06F11/00

    CPC分类号： G11C29/56008 ,  G06F11/2289 ,  G06F11/3409 ,  G11C16/349

    摘要： Discarded memory devices unfit for an original purpose can be reclaimed for reuse for another purpose. The discarded memory devices are tested and evaluated to determine the level of performance degradation therein. A set of an alternate usage and an information encoding scheme to facilitate a reuse of the tested memory device is identified based on the evaluation of the discarded memory device. A memory chip controller may be configured to facilitate usage of reclaimed memory devices by enabling a plurality of encoding schemes therein. Further, a memory device can be configured to facilitate diagnosis of the functionality, and to facilitate usage as a discarded memory unit. Waste due to discarded memory devices can be thereby reduced.

    摘要翻译： 废弃的不适合原始目的的存储设备可以回收再利用用于另一目的。 对废弃的存储器件进行测试和评估，以确定其中性能下降的程度。 基于对废弃的存储器件的评估来识别一组替代使用和信息编码方案，以便于重新使用被测试的存储器件。 存储器芯片控制器可以被配置为通过使能其中的多个编码方案来促进再生存储器件的使用。 此外，存储器装置可以被配置为便于诊断功能，并且便于作为丢弃的存储器单元的使用。 因此可以减少由于废弃的存储器件造成的浪费。

    ADJUSTABLE WRITE BINS FOR MULTI-LEVEL ANALOG MEMORIES
    36.
    发明申请
    ADJUSTABLE WRITE BINS FOR MULTI-LEVEL ANALOG MEMORIES 有权
    用于多级模拟记忆体的可调写文字

    公开(公告)号：US20110069521A1

    公开(公告)日：2011-03-24

    申请号：US12566430

    申请日：2009-09-24

    申请人： Ibrahim M. Elfadel ,  Michele M. Franceschini ,  Luis A. Lastras-Montano ,  Thomas Mittelholzer ,  Mayank Sharma

    发明人： Ibrahim M. Elfadel ,  Michele M. Franceschini ,  Luis A. Lastras-Montano ,  Thomas Mittelholzer ,  Mayank Sharma

    IPC分类号： G11C27/00 ,  G11C11/00

    CPC分类号： G11C8/10 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C27/005 ,  G11C2013/0083

    摘要： An analog memory having adjustable write bins including a system for writing to the memory. The system includes a write apparatus interpreting one or more write control signals, generating a write signal, and applying the write signal at a selected memory location to store a desired content. The selected memory location is subject to data dependent noise and is capable of storing a range of values grouped into “n” bins configured such that the average cost to write to at least “n-1” of the bins is within a threshold of a target cost for the selected analog memory location. The system also includes a read apparatus. The system further includes write control circuitry that includes a write signal selector selecting the one or more write control signals responsive to the desired content, current content of the selected memory location, and a bin associated with the desired content.

    摘要翻译： 具有可调节写入箱的模拟存储器，包括用于向存储器写入的系统。 该系统包括解释一个或多个写入控制信号的写入装置，产生写入信号，以及在选择的存储器位置处施加写入信号以存储所需的内容。 所选择的存储器位置受到数据相关噪声的影响，并且能够存储被分配到“n”个存储槽中的值的范围，其被配置为使得写入至少“n-1”个存储单元的平均成本在 所选模拟存储器位置的目标成本。 该系统还包括读取装置。 该系统还包括写控制电路，其包括响应于期望内容选择一个或多个写入控制信号的写入信号选择器，所选择的存储器位置的当前内容以及与期望内容相关联的存储区。

    Memory cell presetting for improved memory performance
    37.
    发明授权
    Memory cell presetting for improved memory performance 有权
    内存单元预置，以提高内存性能

    公开(公告)号：US08874846B2

    公开(公告)日：2014-10-28

    申请号：US13619451

    申请日：2012-09-14

    申请人： Michele M. Franceschini ,  Ashish Jagmohan ,  John P. Karidis ,  Luis A. Lastras-Montano ,  Moinuddin K. Qureshi

    发明人： Michele M. Franceschini ,  Ashish Jagmohan ,  John P. Karidis ,  Luis A. Lastras-Montano ,  Moinuddin K. Qureshi

    IPC分类号： G06F12/00 ,  G06F12/08

    CPC分类号： G06F12/00 ,  G06F12/08 ,  G06F12/0802 ,  G06F12/0891

    摘要： Memory cell presetting for improved performance including a method for using a computer system to identify a region in a memory. The region includes a plurality of memory cells characterized by a write performance characteristic that has a first expected value when a write operation changes a current state of the memory cells to a desired state of the memory cells and a second expected value when the write operation changes a specified state of the memory cells to the desired state of the memory cells. The second expected value is closer than the first expected value to a desired value of the write performance characteristic. The plurality of memory cells in the region are set to the specified state, and the data is written into the plurality of memory cells responsive to the setting.

    摘要翻译： 用于改进性能的存储单元预设，包括使用计算机系统识别存储器中的区域的方法。 该区域包括多个存储单元，其特征在于当写入操作将存储单元的当前状态改变到存储单元的期望状态时具有第一期望值的写入性能特性，以及当写入操作改变时第二预期值 存储器单元的指定状态到存储器单元的期望状态。 第二期望值比第一期望值更接近写入性能特性的期望值。 区域中的多个存储单元被设置为指定状态，并且响应于该设置将数据写入多个存储单元。

    PROBABILISTIC MULTI-TIER ERROR CORRECTION IN NOT-AND (NAND) FLASH MEMORY
    40.
    发明申请
    PROBABILISTIC MULTI-TIER ERROR CORRECTION IN NOT-AND (NAND) FLASH MEMORY 有权
    非 - 和（NAND）闪存中的概念多层错误校正

    公开(公告)号：US20120144272A1

    公开(公告)日：2012-06-07

    申请号：US12960004

    申请日：2010-12-03

    申请人： Michele M. Franceschini ,  Ashish Jagmohan ,  Luis A. Lastras-Montano ,  Mayank Sharma

    发明人： Michele M. Franceschini ,  Ashish Jagmohan ,  Luis A. Lastras-Montano ,  Mayank Sharma

    IPC分类号： H03M13/05 ,  G06F11/10

    CPC分类号： G06F11/1012 ,  H03M13/2906 ,  H03M13/3715 ,  H03M13/3738

    摘要： Error correction in not-and (NAND) flash memory including a system for retrieving data from memory. The system includes a decoder in communication with a memory. The decoder is for performing a method that includes receiving a codeword stored on a page in the memory, the codeword including data and first-tier check symbols that are generated in response to the data. The method further includes determining that the codeword includes errors that cannot be corrected using the first-tier check symbols, and in response second-tier check symbols are received. The second-tier check symbols are generated in response to receiving the data and to the contents of other pages in the memory that were written prior to the page containing the codeword. The codeword is corrected in response to the second-tier check symbols. The corrected codeword is output.

    摘要翻译： 在非NAND（NAND）闪存中包括用于从存储器检索数据的系统的纠错。 该系统包括与存储器通信的解码器。 解码器用于执行包括接收存储在存储器中的页面上的码字的方法，所述码字包括响应于该数据生成的数据和第一层校验符号。 该方法还包括确定码字包括不能使用第一层校验符号校正的错误，并且响应于接收到第二层校验符号。 响应于接收到包含码字的页面之前写入的数据和存储器中的其他页面的内容，生成第二层校验符号。 响应于第二层校验符号校正码字。 校正的码字被输出。