公开(公告)号：US6097212A

公开(公告)日：2000-08-01

申请号：US948306

申请日：1997-10-09

申请人： Om P. Agrawal ,  Herman M. Chang ,  Bradley A. Sharpe-Geisler ,  Giap H. Tran

发明人： Om P. Agrawal ,  Herman M. Chang ,  Bradley A. Sharpe-Geisler ,  Giap H. Tran

IPC分类号： H03K19/173 ,  H03K19/177 ,  H01L25/00

CPC分类号： H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17748 ,  H03K19/17752 ,  H03K19/17756 ,  H03K19/17792 ,  H03K19/17796 ,  H01L2924/0002

摘要： A Variable Grain Architecture is disclosed wherein Variable Grain Blocks (VGB's) are wedged together in mirror opposition to one another to define super-VGB structures. The super-VGB structures are arranged as a matrix within an FPGA device. Each VGB includes progressive function synthesizing layers for forming more complex function signals by folding together less complex function signals of preceding layers. A function spawning layer containing a set of function spawning lookup tables (LUT's) is provided near the periphery of the corresponding super-VGB structure. In one case, the function spawning layer is L-shaped and includes a symmetrical distribution of Configurable Building Blocks. A signal-acquiring layer interfaces with adjacent interconnect lines to acquire input terms for the LUT's and controls. A decoding layer is interposed between the signal-acquiring layer and the function spawning layer for providing strapping and intercept functions. Each VGB has a common controls section, a wide-gating section and a carry-propagating section. Each super-VGB has a centrally-shared section of longline drivers that may be accessed from any of the constituent VGB's. A diversified spectrum of interconnect lines, including 2xL, 4xL, 8xL and direct connect surround each super-VGB to provide different kinds of interconnect.

公开(公告)号：US5818254A

公开(公告)日：1998-10-06

申请号：US459230

申请日：1995-06-02

申请人： Om P. Agrawal ,  Bradley A. Sharpe-Geisler

发明人： Om P. Agrawal ,  Bradley A. Sharpe-Geisler

IPC分类号： H03K19/177 ,  H03K7/38

CPC分类号： H03K19/17736 ,  H03K19/17704

摘要： A hierarchical switch matrix in a very high-density programmable logic device (CPLD) interconnects a multiplicity of programmable logic blocks in the CPLD. A new level of functionality coupled with high speed is provided by the hierarchical switch matrix. The hierarchical switch matrix includes three levels, a global switch matrix, a segment switch matrix and a block switch matrix. The block switch matrix provides a high speed signal path for signals within a programmable logic block. The segment switch matrix provides a high speed means of communication for signals within a segment, while the global switch matrix provides a high speed path for communication between segments. The hierarchical switch matrix of this invention provides a fixed, path independent, uniform, predictable and deterministic time delay for each group of signals routed through the hierarchical switch matrix.

摘要翻译： 非常高密度可编程逻辑器件（CPLD）中的分层开关矩阵互连了CPLD中的多个可编程逻辑块。 通过分层交换矩阵提供了一个新的功能级别与高速度。 分层交换矩阵包括三个层次，全局交换矩阵，分段交换矩阵和块交换矩阵。 块开关矩阵为可编程逻辑块内的信号提供高速信号路径。 分段开关矩阵为段内的信号提供高速通信装置，而全局开关矩阵为段之间的通信提供高速路径。 本发明的分层交换矩阵为通过分层交换矩阵路由的每组信号提供固定的，路径独立的，均匀的，可预测的和确定性的时间延迟。

公开(公告)号：US5811986A

公开(公告)日：1998-09-22

申请号：US474635

申请日：1995-06-06

申请人： Om P. Agrawal ,  Kerry A. Ilgenstein

发明人： Om P. Agrawal ,  Kerry A. Ilgenstein

IPC分类号： H03K19/173 ,  H03K19/177 ,  H03K7/38

CPC分类号： H03K19/1774 ,  H03K19/17704 ,  H03K19/17716

摘要： A programmable logic device (PLD) cell is used to construct a high density high performance programmable logic device (PLD). The PLD cell includes two programmable logic block cells. The PLD cell also includes an I/O cell and an input macrocell. In addition the PLD cell includes a sub-bank of a programmable output switch matrix bank and a sub-bank of a programmable input switch matrix bank. Each programmable logic block cell includes a multiplicity of product terms. At least one product term in the cluster is programmably available to the cluster. When the product term is disconnected from the cluster, the product term is used for control of the polarity of the logic macrocell output signal or asynchronous functions. Thus, the programmably connectable product term can be used for either synchronous or asynchronous operations. If the programmably connectable and disconnectable product term is connected to the product term cluster, the programmable logic block cell is used for synchronous operations. However, since each product term cluster is associated with a logic macrocell, the logic macrocell can be individually configured for asynchronous operation by simply disconnecting the appropriate product term from the product term cluster and using the product term for the desired asynchronous function. Thus, a single PLD built using the programmable logic block cells supports simultaneously synchronous and asynchronous operations.

摘要翻译： 可编程逻辑器件（PLD）单元用于构建高密度高性能可编程逻辑器件（PLD）。 PLD单元包括两个可编程逻辑块单元。 PLD单元还包括I / O单元和输入宏单元。 此外，PLD单元包括可编程输出开关矩阵组的子组和可编程输入开关矩阵组的子组。 每个可编程逻辑块单元包括多个乘积项。 集群中至少有一个产品术语可编程地可用于集群。 当产品术语与集群断开连接时，产品术语用于控制逻辑宏单元输出信号或异步功能的极性。 因此，可编程可连接产品术语可用于同步或异步操作。 如果可编程可连接和可断开的产品术语连接到产品术语集群，则可编程逻辑块单元用于同步操作。 然而，由于每个产品项集合与逻辑宏单元相关联，所以逻辑宏单元可以通过简单地从产品项集群中断开适当的产品项并使用所需的异步功能的乘积项来单独配置用于异步操作。 因此，使用可编程逻辑块单元构建的单个PLD同时支持同步和异步操作。

公开(公告)号：US5621650A

公开(公告)日：1997-04-15

申请号：US456946

申请日：1995-06-01

申请人： Om P. Agrawal ,  Michael J. Wright

发明人： Om P. Agrawal ,  Michael J. Wright

IPC分类号： H03K19/173 ,  H03K19/177 ,  H03K17/693

CPC分类号： H03K19/17744 ,  H03K19/1737 ,  H03K19/17704

摘要： A method and on-chip architecture are disclosed for multiplexing signals from selected external interconnect buses to chip internal buses such that bus rerouting can be implemented programmably without substantially affecting timing relations between time-parallel signals of a rerouted bus. An on-chip switch matrix is provided having N input lines crossing with M output lines to provide N times M crosspoints. A plurality of substantially less than N times M programmable interconnect switches (PIP's) are distributed symmetrically among the N.multidot.M crosspoints such that a same first number of interconnect switches (PIP's) are found along each of the N input lines thereby providing equal loading on each input line. The plurality of programmable interconnect switches (PIP's) are further distributed among the N.multidot.M crosspoints such that a same second number of interconnect switches (PIP's) are found along each of the M output lines thereby providing equal loading on each output line.

公开(公告)号：US5594365A

公开(公告)日：1997-01-14

申请号：US486174

申请日：1995-06-06

申请人： Om P. Agrawal ,  Jerry D. Moench

发明人： Om P. Agrawal ,  Jerry D. Moench

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17796 ,  H03K19/17704 ,  H03K19/17792

摘要： The programmable logic device (PLD) of this invention includes two or more programmable logic blocks interconnected by a programmable switch matrix that includes a programmable input switch matrix (input switch matrix) and a programmable centralized switch matrix (centralized switch matrix). Each programmable logic block receives input signals only from the centralized switch matrix. The output signals from a programmable logic block are coupled to a plurality of input/output (I/O) pins by an output switch matrix. The output signals from the programmable logic block are also fed directly to the programmable input switch matrix. In addition, an input macrocell couples the signal on an I/O pin driving the input macrocell, i.e., the associated I/O pin, to the programmable input switch matrix. Each programmable logic block includes a programmable logic array, a programmable logic allocator, and programmable logic macrocells. The PLD includes a block clock generation circuit. In the block clock generation circuit, a plurality of programmable block multiplexers provide a plurality of clock signals to a programmable macrocell clock multiplexer in a macrocell of the PLD.

摘要翻译： 本发明的可编程逻辑器件（PLD）包括通过包括可编程输入开关矩阵（输入开关矩阵）和可编程集中式开关矩阵（集中式开关矩阵））的可编程开关矩阵互连的两个或多个可编程逻辑块。 每个可编程逻辑块仅从集中式交换矩阵接收输入信号。 来自可编程逻辑块的输出信号通过输出开关矩阵耦合到多个输入/输出（I / O）引脚。 来自可编程逻辑块的输出信号也直接馈送到可编程输入开关矩阵。 此外，输入宏单元将驱动输入宏单元的I / O引脚上的信号（即，相关联的I / O引脚）耦合到可编程输入开关矩阵。 每个可编程逻辑块包括可编程逻辑阵列，可编程逻辑分配器和可编程逻辑宏单元。 PLD包括块时钟产生电路。 在块时钟发生电路中，多个可编程块多路复用器向PLD的宏小区中的可编程宏小区时钟多路复用器提供多个时钟信号。

公开(公告)号：US5485104A

公开(公告)日：1996-01-16

申请号：US375465

申请日：1995-01-18

申请人： Om P. Agrawal ,  Jerry D. Moench ,  Kerry A. Ilgenstein

发明人： Om P. Agrawal ,  Jerry D. Moench ,  Kerry A. Ilgenstein

IPC分类号： H03K19/173 ,  H03K19/177 ,  H01L25/00

CPC分类号： H03K19/17708 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1774 ,  H03K19/17744

摘要： Each programmable logic device in at least two families of high density segmented programmable array logic device utilizes a programmable switch interconnection matrix to couple an array of symmetric programmable logic blocks. Each programmable logic block includes programmable logic macrocells, programmable input/output macrocells, a logic allocator and a programmable product term array. The programmable switch matrix provides centralized global routing with a fixed path independent delay and decouples the logic macrocells from the product term array. The logic allocator decouples the product term array from the logic macrocells, and the I/O macrocells decouple the logic macrocells from the package I/O pins. The logic allocator steers product terms from the product term array to selected logic macrocells so that no product terms are permanently allocated to a specific logic macrocell. In a first PLD of each family, a first predetermined number of input lines couple the switch matrix to each programmable logic block. In a second PLD of each family, a second predetermined number of input lines couple the switch matrix to each programmable logic block. The number of input lines to each programmable logic block and to the switch matrix are selected to provide a predetermined routability factor. The second family of PLDs has a larger pin to logic ratio than the first family of PLDs.

摘要翻译： 至少两个系列的高密度分段可编程阵列逻辑器件中的每个可编程逻辑器件利用可编程开关互连矩阵来耦合对称可编程逻辑块阵列。 每个可编程逻辑块包括可编程逻辑宏单元，可编程输入/输出宏单元，逻辑分配器和可编程产品项阵列。 可编程开关矩阵提供具有固定路径独立延迟的集中式全局路由，并将逻辑宏单元与产品项阵列分离。 逻辑分配器将产品项阵列与逻辑宏单元分离，并且I / O宏单元将逻辑宏单元与封装I / O引脚分离。 逻辑分配器将产品术语从产品术语数组转向选定的逻辑宏单元，使得不将产品术语永久分配给特定的逻辑宏单元。 在每个系列的第一PLD中，第一预定数量的输入线将开关矩阵耦合到每个可编程逻辑块。 在每个系列的第二PLD中，第二预定数量的输入线将开关矩阵耦合到每个可编程逻辑块。 选择到每个可编程逻辑块和开关矩阵的输入线的数量以提供预定的可布线因子。 第二系列PLD具有比第一个PLD系列更大的引脚与逻辑比。

公开(公告)号：US5349670A

公开(公告)日：1994-09-20

申请号：US149029

申请日：1993-11-08

申请人： Om P. Agrawal ,  Arthur H. Khu ,  Kapil Shankar

发明人： Om P. Agrawal ,  Arthur H. Khu ,  Kapil Shankar

IPC分类号： G05B19/045 ,  G06F9/00

CPC分类号： G05B19/045 ,  G05B2219/21115

摘要： An integrated circuit programmable sequencing element apparatus on a single chip is provided which includes a PROM including first signal receiving circuitry and second signal providing circuitry; at least one feedback signal providing circuitry responsive to at least one second signal for providing at least one feedback signal; at least one input signal providing circuitry for providing at least one input signal; at least one control signal providing circuitry for providing at least one control signal; at least one programmable sequencing element circuitry for receiving said at least one control signal and the at least one input signal and for providing at least one programmable sequencing element signal; and selection circuitry for selecting at least between the at least one programmable sequencing element signal and the at least one feedback signal and for providing at least one selected signal to the first signal receiving circuitry.

摘要翻译： 提供了在单个芯片上的集成电路可编程排序元件装置，其包括包括第一信号接收电路和第二信号提供电路的PROM; 至少一个反馈信号提供电路响应于至少一个第二信号以提供至少一个反馈信号; 至少一个输入信号提供电路，用于提供至少一个输入信号; 至少一个控制信号提供电路，用于提供至少一个控制信号; 至少一个可编程排序元件电路，用于接收所述至少一个控制信号和所述至少一个输入信号，并用于提供至少一个可编程序列元件信号; 以及选择电路，用于至少在所述至少一个可编程排序元件信号和所述至少一个反馈信号之间进行选择，并用于向所述第一信号接收电路提供至少一个所选择的信号。

公开(公告)号：US5349544A

公开(公告)日：1994-09-20

申请号：US207317

申请日：1988-06-15

申请人： Michael J. Wright ,  Om P. Agrawal

发明人： Michael J. Wright ,  Om P. Agrawal

IPC分类号： H03K19/177 ,  H03L7/06 ,  H03L7/183 ,  G06J1/00

CPC分类号： H03L7/183

摘要： A PLL is integrated on the same chip as a programmable logic circuit and interconnected therewith in any of several useful ways. In one aspect of the invention, the output frequency of the PLL may be connected to the clock input of registers in the programmable logic circuit. If the PLL performs frequency multiplication, the chip then becomes a high-speed state machine synchronized to a lower-frequency input clock. In another aspect of the invention, the signal present at different parts of the phase lock loop may be provided to inputs of the programmable logic circuit. In another aspect, outputs of the programmable logic circuit may be used to control the operation and/or characteristics of various components in the PLL. For example, if a counter is included in the phase lock loop for causing the loop to generate a frequency multiple of the input signal, the counter may be made programmable according to outputs of the state machine. Similarly, the characteristics of the phase detector or loop filter may be dynamically adjusted according to outputs of the state machine. In yet another aspect of the invention, an output of the programmable logic circuit is, or is used to generate, one of the inputs to the phase detector in the PLL.

摘要翻译： PLL与可编程逻辑电路集成在同一个芯片上，并以几种有用的方式进行互连。 在本发明的一个方面，PLL的输出频率可以连接到可编程逻辑电路中的寄存器的时钟输入。 如果PLL执行倍频，芯片就成为与低频输入时钟同步的高速状态机。 在本发明的另一方面，存在于锁相环的不同部分的信号可以被提供给可编程逻辑电路的输入端。 在另一方面，可编程逻辑电路的输出可用于控制PLL中的各种组件的操作和/或特性。 例如，如果在锁相环中包括计数器以使环路产生输入信号的频率倍数，则可以根据状态机的输出使计数器可编程。 类似地，可以根据状态机的输出来动态调整相位检测器或环路滤波器的特性。 在本发明的另一方面，可编程逻辑电路的输出是或用于产生PLL中的相位检测器的输入之一。

公开(公告)号：US5027315A

公开(公告)日：1991-06-25

申请号：US401528

申请日：1989-08-30

申请人： Om P. Agrawal ,  Joseph A. Brcich

发明人： Om P. Agrawal ,  Joseph A. Brcich

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/1733 ,  H03K19/17716

摘要： The present invention provides an output logic macrocell for controlling configuration of an output for an integrated circuit wich provides a logic signal including a register responsive to a clock signal for latching the logic signal to provide a registered signal. An output selector receives both the logic signal and the registered signal and selects responsive to an output select signal, either the logic signal or the registered signal. A feedback path provides a feedback signal as data which is selected by a feedback selector responsive to a feedback select signal for selecting the logic signal or the registered signal as the feedback signal. Further, a clock signal enable circuit, responsive to a clock enable signal, enables or disables the clock signal to clock the register. Accordingly, the register, the output selector, the feedback path, and the clock enable circuit are all dynamically controllable by respective control signals.

摘要翻译： 本发明提供一种用于控制集成电路的输出配置的输出逻辑宏单元，其提供包括响应于时钟信号的寄存器的逻辑信号，用于锁存逻辑信号以提供注册信号。 输出选择器接收逻辑信号和注册信号，并且响应输出选择信号选择逻辑信号或登记信号。 反馈路径提供反馈信号作为响应于用于选择逻辑信号或注册信号作为反馈信号的反馈选择信号的反馈选择器选择的数据。 此外，响应于时钟使能信号的时钟信号使能电路启用或禁用时钟信号来对寄存器进行时钟。 因此，寄存器，输出选择器，反馈路径和时钟使能电路都可以通过相应的控制信号动态地控制。

公开(公告)号：US5015884A

公开(公告)日：1991-05-14

申请号：US490808

申请日：1990-03-07

申请人： Om P. Agrawal ,  George H. Landers ,  Nicholas A. Schmitz ,  Jerry D. Moench ,  Kerry A. Ilgenstein

发明人： Om P. Agrawal ,  George H. Landers ,  Nicholas A. Schmitz ,  Jerry D. Moench ,  Kerry A. Ilgenstein

IPC分类号： H01L21/82 ,  H03K19/177

CPC分类号： H03K19/17708 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1774 ,  H03K19/17744

摘要： A high density segmented programmable array logic device utilizes a programmable switch interconnection matrix to couple an array of symmetric programmable logic blocks. Each programmable logic block includes programmable logic macrocells, programmable input/output macrocells, a logic allocator and a programmable product term array. Further, the switch matrix provides centralized global routing with a fixed path independent delay. The programmable switch interconnection matrix decouples the logic macrocells from the product term array. The logic allocator decouples the product term array from the logic macrocells, and the I/O marcrocells decouple the logic macrocells from the package I/O pins. Thus, the architecture of this invention is easily scalable to higher density devices without compromising speed. The logic allocator steers product terms from the product term array to selected logic macrocells so that no product terms are permanently allocated to a specific logic macrocell.

摘要翻译： 高密度分段可编程阵列逻辑器件利用可编程开关互连矩阵来耦合对称可编程逻辑块阵列。 每个可编程逻辑块包括可编程逻辑宏单元，可编程输入/输出宏单元，逻辑分配器和可编程产品项阵列。 此外，交换矩阵提供具有固定路径独立延迟的集中式全局路由。 可编程开关互连矩阵将逻辑宏单元与产品项阵列分离。 逻辑分配器将产品项阵列与逻辑宏单元分离，I / O马尔克罗尔将逻辑宏单元与封装I / O引脚分离。 因此，本发明的架构可以容易地扩展到更高密度的设备而不会影响速度。 逻辑分配器将产品术语从产品术语数组转向选定的逻辑宏单元，使得不将产品术语永久分配给特定的逻辑宏单元。