公开(公告)号：US06900092B2

公开(公告)日：2005-05-31

申请号：US10183336

申请日：2002-06-27

申请人： Atul C. Ajmera ,  Dominic J. Schepis ,  Michael D. Steigerwalt

发明人： Atul C. Ajmera ,  Dominic J. Schepis ,  Michael D. Steigerwalt

IPC分类号： H01L21/20 ,  H01L21/336 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/31 ,  H01L21/3205

CPC分类号： H01L29/7834 ,  H01L21/02532 ,  H01L21/02639 ,  H01L29/66628 ,  Y10S438/976

摘要： The present invention provides a method of formed a nitrided surface layer atop a polysilicon gate electrode that inhibits the growth of an epi silicon layer thereon. Specifically, the method of the present invention includes the steps of: forming a polysilicon layer atop a gate dielectric layer, forming a nitrided surface layer on the polysilicon layer; selectively removing portions of the nitrided surface layer and the polysilicon layer stopping on the gate dielectric layer, while leaving a patterned stack of the nitrided surface layer and the polysilicon layer on the gate dielectric layer; forming sidewall spacers on at least exposed vertical sidewalls of polysilicon layer; removing portions of the gate dielectric layer not protected by the sidewall spacers; and growing an epi silicon layer on exposed horizontal surfaces of an underlying semiconductor substrate.

摘要翻译： 本发明提供一种在多晶硅栅电极顶上形成氮化表面层的方法，该多晶硅栅电极抑制其上的外延硅层的生长。 具体地说，本发明的方法包括以下步骤：在栅极电介质层的顶部形成多晶硅层，在多晶硅层上形成氮化表面层; 选择性地去除氮化表面层和多晶硅层的部分，停留在栅极介电层上，同时在栅极电介质层上留下图案化的氮化表面层和多晶硅层的叠层; 在多晶硅层的至少暴露的垂直侧壁上形成侧壁间隔物; 去除不被侧壁间隔物保护的栅极电介质层的部分; 以及在下面的半导体衬底的暴露的水平表面上生长外延硅层。

公开(公告)号：US06808974B2

公开(公告)日：2004-10-26

申请号：US09859021

申请日：2001-05-15

申请人： Heemyong Park ,  Dominic J. Schepis ,  Fariborz Assaderaghi

发明人： Heemyong Park ,  Dominic J. Schepis ,  Fariborz Assaderaghi

IPC分类号： H01L218238

CPC分类号： H01L29/6659 ,  H01L21/823814 ,  H01L21/823842

摘要： A method is provided for maximizing activation of a gate electrode while preventing source and drain regions from being excessively doped. The gate electrode is partially doped when exposed the source/drain implantation step. Then, the gate electrode is fully doped by the selective implantation step while the source/drain regions are blocked. Separate annealing steps are provided subsequent to the gate doping step and the source and drain implantation step.

摘要翻译： 提供一种用于使栅电极的激活最大化同时防止源区和漏区被过度掺杂的方法。 当暴露源极/漏极注入步骤时，栅电极被部分掺杂。 然后，通过选择性注入步骤完全掺杂栅电极，同时源极/漏极区域被阻挡。 在栅极掺杂步骤和源极和漏极注入步骤之后提供单独的退火步骤。

公开(公告)号：US06563173B2

公开(公告)日：2003-05-13

申请号：US09859146

申请日：2001-05-16

申请人： Ronald J. Bolam ,  Subhash B. Kulkarni ,  Dominic J. Schepis

发明人： Ronald J. Bolam ,  Subhash B. Kulkarni ,  Dominic J. Schepis

IPC分类号： H01L2900

CPC分类号： H01L29/66772 ,  H01L21/743 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78636 ,  H01L29/78648

摘要： An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The isolation barrier extends through the silicon layer and the oxide layer, and partially into the substrate, to block impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contact—which define an active chip area inside the isolation barrier. A method of manufacturing the SOI chip is also disclosed.

公开(公告)号：US06541317B2

公开(公告)日：2003-04-01

申请号：US09848466

申请日：2001-05-03

申请人： K. Paul Muller ,  Dominic J. Schepis ,  Ghavam G. Shahidi

发明人： K. Paul Muller ,  Dominic J. Schepis ,  Ghavam G. Shahidi

IPC分类号： H01L2100

CPC分类号： H01L29/66553 ,  H01L21/2257 ,  H01L21/7624 ,  H01L29/41766 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/66621

摘要： Steep concentration gradients are achieved in semiconductor device of small sizes by using implanted polycrystalline material such as polysilicon as a solid diffusion source. Rapid diffusion of impurities along grain boundaries relative to diffusion rates in monocrystalline materials provides a substantially constant impurity concentration at the interface between polycrystalline material and monocrystalline material. Steepness of the impurity concentration gradient is thus effectively scaled as transistor size is decreased to counter increased short channel and other deleterious effects.

公开(公告)号：US06440807B1

公开(公告)日：2002-08-27

申请号：US09882095

申请日：2001-06-15

申请人： Atul C. Ajmera ,  Dominic J. Schepis ,  Michael D. Steigerwalt

发明人： Atul C. Ajmera ,  Dominic J. Schepis ,  Michael D. Steigerwalt

IPC分类号： H01L21336

CPC分类号： H01L29/7834 ,  H01L21/02532 ,  H01L21/02639 ,  H01L29/66628 ,  Y10S438/976

摘要： The present invention provides a method of formed a nitrided surface layer atop a polysilicon gate electrode that inhibits the growth of an epi silicon layer thereon. Specifically, the method of the present invention includes the steps of: forming a polysilicon layer atop a gate dielectric layer, forming a nitrided surface layer on the polysilicon layer; selectively removing portions of the nitrided surface layer and the polysilicon layer stopping on the gate dielectric layer, while leaving a patterned stack of the nitrided surface layer and the polysilicon layer on the gate dielectric layer; forming sidewall spacers on at least exposed vertical sidewalls of polysilicon layer; removing portions of the gate dielectric layer not protected by the sidewall spacers; and growing an epi silicon layer on exposed horizontal surfaces of an underlying semiconductor substrate.

摘要翻译： 本发明提供一种在多晶硅栅电极顶上形成氮化表面层的方法，该多晶硅栅电极抑制其上的外延硅层的生长。 具体地说，本发明的方法包括以下步骤：在栅极电介质层的顶部形成多晶硅层，在多晶硅层上形成氮化表面层; 选择性地去除氮化表面层和多晶硅层的部分，停留在栅极介电层上，同时在栅极电介质层上留下图案化的氮化表面层和多晶硅层的叠层; 在多晶硅层的至少暴露的垂直侧壁上形成侧壁间隔物; 去除不被侧壁间隔物保护的栅极电介质层的部分; 以及在下面的半导体衬底的暴露的水平表面上生长外延硅层。

公开(公告)号：US06404014B1

公开(公告)日：2002-06-11

申请号：US09708337

申请日：2000-11-08

申请人： Effendi Leobandung ,  Devendra K. Sadana ,  Dominic J. Schepis ,  Ghavam Shahidi

发明人： Effendi Leobandung ,  Devendra K. Sadana ,  Dominic J. Schepis ,  Ghavam Shahidi

IPC分类号： H01L2701

CPC分类号： H01L21/76264 ,  H01L21/762 ,  H01L21/76278

摘要： A planar silicon-on-insulator (SOI) structure and a process for fabricating the structure. The SOI structure has a silicon wafer, an oxide layer, and a silicon layer. Trenches are formed, extending from the top surface of the structure to the silicon wafer, and are filled with a semiconductor. The trenches have a top, a bottom, and side walls. The side walls have side-wall silicon portions. The side-wall silicon portions of the trench side walls are covered by trench side-wall oxide layers. A protective side wall extends over the trench side walls and trench side-wall oxide layers from the trench top to the trench bottom.

摘要翻译： 一种平面绝缘体上硅（SOI）结构及其制造方法。 SOI结构具有硅晶片，氧化物层和硅层。 形成从结构的顶表面延伸到硅晶片并且填充有半导体的沟槽。 沟槽有顶部，底部和侧壁。 侧壁具有侧壁硅部分。 沟槽侧壁的侧壁硅部分被沟槽侧壁氧化物层覆盖。 保护侧壁从沟槽顶部到沟槽底部在沟槽侧壁和沟槽侧壁氧化物层上延伸。

公开(公告)号：US06387742B2

公开(公告)日：2002-05-14

申请号：US09862451

申请日：2001-05-23

申请人： Robert J. Gauthier, Jr. ,  Dominic J. Schepis ,  William R. Tonti ,  Steven H. Voldman

发明人： Robert J. Gauthier, Jr. ,  Dominic J. Schepis ,  William R. Tonti ,  Steven H. Voldman

IPC分类号： H01L21336

CPC分类号： H01L29/78648 ,  H01L21/76264 ,  H01L21/76286 ,  H01L21/763 ,  H01L23/3677 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： Silicon is formed at selected locations on a substrate during fabrication of selected electronic components. A dielectric separation region is formed within the top silicon layer, and filled with a thermally conductive material. A liner material may be optionally deposited prior to depositing the thermally conductive material. In a second embodiment, a horizontal layer of thermally conductive material is also deposited in an oxide layer or bulk silicon layer below the top layer of silicon.

摘要翻译： 在选择的电子部件的制造期间，在基板上的选定位置处形成硅。 介电分离区形成在顶层硅层内，并填充有导热材料。 衬里材料可以在沉积导热材料之前任选地沉积。 在第二实施例中，水平导热材料层也沉积在硅顶层之下的氧化物层或体硅层中。

公开(公告)号：US06339005B1

公开(公告)日：2002-01-15

申请号：US09425394

申请日：1999-10-22

申请人： Andres Bryant ,  Jerome B. Lasky ,  Effendi Leobandung ,  Dominic J. Schepis

发明人： Andres Bryant ,  Jerome B. Lasky ,  Effendi Leobandung ,  Dominic J. Schepis

IPC分类号： H01L21336

CPC分类号： H01L29/66643 ,  H01L29/458 ,  H01L29/6653 ,  H01L29/66659 ,  H01L29/66772 ,  H01L29/7839 ,  H01L29/78609 ,  H01L29/78612 ,  H01L29/78621 ,  H01L29/78624 ,  H01L29/812

摘要： A silicon on insulator transistor is disclosed which has a Schottky contact to the body. The Schottky contact may be formed on the source and/or drain side of the gate conductor. A spacer, with at least a part thereof being disposable, is formed on the sidewalls of the gate conductor. Extension regions are provided in the substrate which extend under the spacer and the gate conductor. Source and drain diffusion regions are implanted into the substrate adjacent to the extension regions. The disposable part of the spacer is then removed to expose a portion of the extension region. A metal layer is formed at least in the extension regions, resulting in the Schottky contact.

摘要翻译： 公开了一种绝缘体上硅晶体管，其具有与身体的肖特基接触。 肖特基接触可以形成在栅极导体的源极和/或漏极侧。 在栅极导体的侧壁上形成有至少一部分是一次性的间隔物。 延伸区域设置在衬底下延伸在间隔物和栅极导体之下。 源极和漏极扩散区域被注入邻近延伸区域的衬底中。 然后移除间隔件的一次性部分以暴露延伸区域的一部分。 至少在延伸区域中形成金属层，导致肖特基接触。

公开(公告)号：US06255145B1

公开(公告)日：2001-07-03

申请号：US09227696

申请日：1999-01-08

申请人： Atul Ajmera ,  Devendra K. Sadana ,  Dominic J. Schepis

发明人： Atul Ajmera ,  Devendra K. Sadana ,  Dominic J. Schepis

IPC分类号： H01L2100

CPC分类号： H01L21/76264 ,  H01L21/26533 ,  H01L21/2658 ,  H01L21/266 ,  H01L21/3086 ,  H01L21/76267 ,  H01L21/76283

摘要： A process for forming a planar silicon-on-insulator (SOI) substrate comprising a patterned SOI region and a bulk region, wherein the substrate is free of transitional defects. The process comprises removing the transitional defects by creating a self-aligned trench adjacent the SOI region between the SOI region and the bulk region.

摘要翻译： 一种用于形成包括图案化SOI区域和体区域的平面绝缘体上硅（SOI）衬底的工艺，其中所述衬底没有过渡缺陷。 该过程包括通过在SOI区域和体区域之间产生邻近SOI区域的自对准沟槽来去除过渡缺陷。

公开(公告)号：US08575655B2

公开(公告)日：2013-11-05

申请号：US13431328

申请日：2012-03-27

申请人： Stephen W. Bedell ,  Ashima B. Chakravarti ,  Michael P. Chudzik ,  Judson R. Holt ,  Dominic J. Schepis

发明人： Stephen W. Bedell ,  Ashima B. Chakravarti ,  Michael P. Chudzik ,  Judson R. Holt ,  Dominic J. Schepis

IPC分类号： H01L29/66

CPC分类号： H01L29/1054 ,  H01L21/0237 ,  H01L21/02532 ,  H01L21/02612 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/7833

摘要： Various techniques for changing the workfunction of the substrate by using a SiGe channel which, in turn, changes the bandgap favorably for a p-type metal oxide semiconductor field effect transistors (pMOSFETs) are disclosed. In the various techniques, a SiGe film that includes a low doped SiGe region above a more highly doped SiGe region to allow the appropriate threshold voltage (Vt) for pMOSFET devices while preventing pitting, roughness and thinning of the SiGe film during subsequent cleans and processing is provided.

摘要翻译： 公开了通过使用SiGe通道来改变衬底的功函数的各种技术，其又有利于改变p型金属氧化物半导体场效应晶体管（pMOSFET）的带隙。 在各种技术中，SiGe膜包括在更高掺杂的SiGe区域上方的低掺杂SiGe区域，以允许pMOSFET器件的适当阈值电压（Vt），同时防止随后的清洁和处理期间SiGe膜的点蚀，粗糙度和变薄 被提供。