公开(公告)号：US07102952B2

公开(公告)日：2006-09-05

申请号：US10915036

申请日：2004-08-10

申请人： Chan-Yong Lee ,  Jung-Hwa Lee

发明人： Chan-Yong Lee ,  Jung-Hwa Lee

IPC分类号： G11C5/14

CPC分类号： G11C7/1069 ,  G11C5/14 ,  G11C7/1012 ,  G11C7/1051

摘要： A semiconductor memory device having a data read path maintains a higher power voltage supplied to an input/output sense amplifier in the input/output path, through which data passes during a data read operation, than the voltage supplied to other circuit components in the data read path, thereby achieving a high data read speed.

摘要翻译： 具有数据读取路径的半导体存储器件在数据读取操作期间保持提供给输入/输出读出放大器的输入/输出读出放大器的电压高于提供给数据中的其它电路元件的电压 读取路径，从而实现高数据读取速度。

公开(公告)号：US06058064A

公开(公告)日：2000-05-02

申请号：US145905

申请日：1998-09-02

申请人： Jung-Hwa Lee

发明人： Jung-Hwa Lee

IPC分类号： G11C11/409 ,  G11C7/10 ,  G11C7/18 ,  G11C11/401 ,  G11C11/4096 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C7/18 ,  G11C11/4096 ,  G11C11/4097 ,  G11C7/1048 ,  H01L27/10897

摘要： Disclosed herein is a semiconductor memory device which comprises a memory cell array having a plurality of memory cells and a plurality of bit line pairs connected to the memory cells. The device has two data line pairs corresponding to the memory cell array. Furthermore, the device comprises a plurality of selecting transistors connected to the bit line pairs and selecting two bit line pairs to connect the two selected bit line pairs to the two data line pairs in response to a column selection signal. The selecting transistors corresponding to the column selection signal are laid out to share source/drain to data line contacts with contiguous those to be selected by another column selection signal.

摘要翻译： 本文公开了一种半导体存储器件，其包括具有多个存储器单元的存储单元阵列和连接到存储器单元的多个位线对。 该设备具有对应于存储单元阵列的两条数据线对。 此外，该装置包括连接到位线对的多个选择晶体管，并且响应于列选择信号选择两个位线对以将两个所选位线对连接到两个数据线对。 对应于列选择信号的选择晶体管布置成将数据线触点与要由另一列选择信号选择的相邻的数据线触点共享。

公开(公告)号：US5978247A

公开(公告)日：1999-11-02

申请号：US186026

申请日：1998-11-04

申请人： Jung-Hwa Lee

发明人： Jung-Hwa Lee

IPC分类号： H01L21/822 ,  G11C7/18 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4097 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/092 ,  H01L27/108 ,  G11C5/06

CPC分类号： G11C7/18 ,  G11C11/4097 ,  H01L27/10897

摘要： A layout for a semiconductor memory device with a triple well structure, comprises a plurality of memory cell regions arranged in a matrix, a plurality of first circuit regions respectively arranged between adjacent ones of the memory cell regions along the first direction and each having the circuits to code and drive the word lines of corresponding memory cell region, a plurality of second circuit regions respectively arranged between adjacent ones of the memory cell regions in the second direction perpendicular to the first direction and each having the circuit to sense the bit line of corresponding bit line, a plurality of third circuit regions respectively arranged between adjacent ones of the first and second circuit regions, first drive elements applied with at least two well-bias voltages to drive the circuits of the first circuit regions, and second drive elements applied with another well-bias voltage to drive the circuit of the second circuit regions, wherein the first and second drive elements are respectively arranged in two adjacent ones of the third circuit regions.

摘要翻译： 具有三重阱结构的半导体存储器件的布局包括以矩阵形式布置的多个存储单元区域，沿着第一方向分别布置在相邻存储单元区域之间的多个第一电路区域，并且每个具有电路 对相应的存储单元区域的字线进行编码和驱动，在与第一方向垂直的第二方向上分别布置在相邻的存储单元区域之间的多个第二电路区域，并且每个具有用于感测对应的存储单元区域的位线的电路 分别布置在相邻的第一和第二电路区域之间的多个第三电路区域，施加至少两个阱偏置电压的第一驱动元件以驱动第一电路区域的电路，并且第二驱动元件被施加 另一个良好的偏置电压来驱动第二电路区域的电路，其中第一和第二电路区域 偏移驱动元件分别布置在两个相邻的第三电路区域中。

公开(公告)号：US5812466A

公开(公告)日：1998-09-22

申请号：US724798

申请日：1996-10-02

申请人： Jung-Hwa Lee ,  Jin-Man Han ,  Dong-Il Seo

发明人： Jung-Hwa Lee ,  Jin-Man Han ,  Dong-Il Seo

IPC分类号： G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/70

摘要： The present invention relates to a semiconductor memory device incorporating a column redundancy circuit using a decoded fuse. The column redundancy circuit is capable of designating a repaired address during a parallel test mode of memory operation when an address input is a "don't care," and it is particularly useful in a multiple input/output memory architecture which uses one column select per I/O line. The column redundancy circuit includes: transmitting means comprised of the data input/output lines for transmitting the data of the memory cell; column decoder and input/output control circuits connected to the transmitting means and decoding a column address input to input data; a circuit connected to the transmitting means and outputting a given signal to the column decoder and input/output control circuits in response to a plurality of output signals output from fuses and a signal for controlling the transmitting means; a plurality of decoded fuse circuits, the levels of which are determined by one fuse connected to the circuit; multiplexers for selectively transmitting data from one of the data input/output lines to a specific data bus line among a plurality of data bus lines; and a decoding circuit which receives the outputs of the decoded fuse circuits and generates a redundancy signal.

摘要翻译： 本发明涉及一种结合使用解码保险丝的列冗余电路的半导体存储器件。 当地址输入为“无关”时，列冗余电路能够在存储器操作的并行测试模式下指定修复的地址，并且在使用一列选择的多输入/输出存储器架构中特别有用 每个I / O线。 列冗余电路包括：发送装置，包括用于发送存储单元的数据的数据输入/输出线; 列解码器和连接到发送装置的输入/输出控制电路，并且将输入的列地址解码为输入数据; 连接到发送装置的电路，响应于从保险丝输出的多个输出信号和用于控制发送装置的信号，将给定信号输出到列解码器和输入/输出控制电路; 多个解码熔丝电路，其电平由连接到电路的一个熔丝确定; 多路复用器，用于选择性地将数据从数据输入/输出线之一发送到多条数据总线之间的特定数据总线; 以及解码电路，其接收解码的熔丝电路的输出并产生冗余信号。

公开(公告)号：US5726939A

公开(公告)日：1998-03-10

申请号：US668952

申请日：1996-06-24

申请人： Soo-In Cho ,  Jung-Hwa Lee

发明人： Soo-In Cho ,  Jung-Hwa Lee

IPC分类号： G11C11/401 ,  G11C8/12 ,  G11C29/00 ,  G11C29/34 ,  G11C13/00

CPC分类号： G11C8/12

摘要： The time required for testing high-density semiconductor memory devices is reduced by circuits and methodology for rapidly writing test data bits into the memory array. A common word line enable signal is arranged to turn on all of the word lines in the array simultaneously. Test data bits are applied to the array by gating them onto the I/O lines so that separate test bit lines are not required. A fast test enable signal gates the test bits onto the I/O lines in all columns of the array simultaneously, so that all of the memory cells receive test bits at one time. The new circuitry has the further advantages of reduced area and capacitance, the latter further contributing to reducing the test data write time.

摘要翻译： 通过用于将测试数据位快速写入存储器阵列的电路和方法来减少测试高密度半导体存储器件所需的时间。 公共字线使能信号被布置成同时打开阵列中的所有字线。 测试数据位通过将它们门控到I / O线上来应用于阵列，以便不需要单独的测试位线。 快速测试使能信号同时将测试位门控在阵列的所有列中的I / O线上，以便所有存储单元一次接收测试位。 新电路具有减小面积和电容的进一步优点，后者进一步有助于减少测试数据写入时间。