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    Semiconductor memory device having fast writing circuit for test thereof
    1.
    发明授权
    Semiconductor memory device having fast writing circuit for test thereof 失效
    具有用于测试的快速写入电路的半导体存储器件

    公开(公告)号：US5726939A

    公开(公告)日：1998-03-10

    申请号：US668952

    申请日：1996-06-24

    申请人： Soo-In Cho ,  Jung-Hwa Lee

    发明人： Soo-In Cho ,  Jung-Hwa Lee

    IPC分类号： G11C11/401 ,  G11C8/12 ,  G11C29/00 ,  G11C29/34 ,  G11C13/00

    CPC分类号： G11C8/12

    摘要： The time required for testing high-density semiconductor memory devices is reduced by circuits and methodology for rapidly writing test data bits into the memory array. A common word line enable signal is arranged to turn on all of the word lines in the array simultaneously. Test data bits are applied to the array by gating them onto the I/O lines so that separate test bit lines are not required. A fast test enable signal gates the test bits onto the I/O lines in all columns of the array simultaneously, so that all of the memory cells receive test bits at one time. The new circuitry has the further advantages of reduced area and capacitance, the latter further contributing to reducing the test data write time.

    摘要翻译： 通过用于将测试数据位快速写入存储器阵列的电路和方法来减少测试高密度半导体存储器件所需的时间。 公共字线使能信号被布置成同时打开阵列中的所有字线。 测试数据位通过将它们门控到I / O线上来应用于阵列，以便不需要单独的测试位线。 快速测试使能信号同时将测试位门控在阵列的所有列中的I / O线上，以便所有存储单元一次接收测试位。 新电路具有减小面积和电容的进一步优点，后者进一步有助于减少测试数据写入时间。

    Data output buffer control circuit for a semiconductor memory device
    2.
    发明授权
    Data output buffer control circuit for a semiconductor memory device 失效
    用于半导体存储器件的数据输出缓冲器控制电路

    公开(公告)号：US6094376A

    公开(公告)日：2000-07-25

    申请号：US998287

    申请日：1997-12-24

    申请人： Pil-Soon Park ,  Kyung-Woo Kang ,  Soo-In Cho

    发明人： Pil-Soon Park ,  Kyung-Woo Kang ,  Soo-In Cho

    IPC分类号： G11C11/417 ,  G11C7/10 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G11C16/04

    CPC分类号： G11C7/1051

    摘要： A data output buffer control circuit for a semiconductor memory device assures a column address setup time and a valid data setup time in EDO mode by eliminating short glitches in the data output buffer. The circuit assures the column address setup time by disabling the data output buffer for a predetermined period of time after an address transition, regardless of the state of a column address strobe signal. The circuit assures the setup time for valid data by sensing when the address is set up relative to when the column address strobe signal is activated, and then enabling the data output buffer so as to maintain invalid data in the data output buffer long enough to prevent a short glitch in the data output buffer if the column address is set up before the column address strobe signal is activated. The circuit includes a pulse generator for generating a pulse signal each time it senses a column address transition, and a latch circuit for combining the pulse signal with the column address strobe signal so as to generate a buffer control signal for enabling and disabling the data output buffer.

    摘要翻译： 用于半导体存储器件的数据输出缓冲器控制电路通过消除数据输出缓冲器中的短毛刺来确保EDO模式下的列地址建立时间和有效的数据建立时间。 该电路通过在地址转换之后的预定时间段禁用数据输出缓冲器来确保列地址建立时间，而不管列地址选通信号的状态如何。 电路通过检测地址是否相对于列地址选通信号被激活而设置的时间来保证有效数据的建立时间，然后启用数据输出缓冲器，以便在数据输出缓冲器中保持足够长的时间以防止 如果在列地址选通信号被激活之前设置了列地址，则数据输出缓冲器中的短暂毛刺。 电路包括用于每次检测列地址转换时产生脉冲信号的脉冲发生器和用于将脉冲信号与列地址选通信号组合的锁存电路，以便产生用于启用和禁用数据输出的缓冲器控制信号 缓冲。

    Semiconductor memory device
    3.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5610869A

    公开(公告)日：1997-03-11

    申请号：US511815

    申请日：1995-08-07

    申请人： Seung-Moon Yoo ,  Ejaz ul Haq ,  Yun-Ho Choi ,  Soo-In Cho ,  Dae-Je Chin ,  Nam-Soo Kang ,  Seung-Hun Lee

    发明人： Seung-Moon Yoo ,  Ejaz ul Haq ,  Yun-Ho Choi ,  Soo-In Cho ,  Dae-Je Chin ,  Nam-Soo Kang ,  Seung-Hun Lee

    IPC分类号： G11C5/14 ,  H02M3/07 ,  G11C13/00

    CPC分类号： H02M3/07 ,  G11C5/145

    摘要： A semiconductor memory device stably operates over a wide range of the power supply voltage by including a power supply voltage level detector for generating detecting signals according to predetermined levels of the power supply voltage and an oscillator for generating a frequency-controlled oscillation pulse whose frequency is changeable according to the detecting signals. Thus, a boosting ratio of a boosting circuit, the refresh period of a refresh circuit and the substrate voltage of a substrate voltage generator can be adaptively changeable according to the variation of the power supply voltage.

    摘要翻译： 半导体存储器件通过包括用于根据电源电压的预定电平产生检测信号的电源电压电平检测器和用于产生频率为...的频率控制的振荡脉冲的振荡器，稳定地在宽范围的电源电压下工作 根据检测信号可变。 因此，升压电路的升压比，刷新电路的刷新周期和基板电压发生器的基板电压可以根据电源电压的变化自适应地变化。

    Method and circuit for testing a semiconductor memory device operating at high frequency
    4.
    发明授权
    Method and circuit for testing a semiconductor memory device operating at high frequency 失效
    用于测试高频工作的半导体存储器件的方法和电路

    公开(公告)号：US5933379A

    公开(公告)日：1999-08-03

    申请号：US52053

    申请日：1998-03-30

    申请人： Churoo Park ,  Soo-In Cho

    发明人： Churoo Park ,  Soo-In Cho

    IPC分类号： G11C29/50 ,  G11C29/56 ,  G11C7/00

    CPC分类号： G11C29/50 ,  G11C29/56 ,  G11C11/401

    摘要： A circuit for testing a semiconductor memory device comprises a latency controller for controlling the latency of the external clock signal, an internal column address generator for generating a column address signal in the memory device, and a mode register for generating a mode signal. The circuit for testing semiconductor memory devices also includes a column address decoder for decoding the output address signal of the internal column address generator, a memory cell for reading or writing data, an input/output control unit for controlling the data input/output of the memory cell according to the output signal of the latency controller, a data input buffer, and a data output buffer. Further provided are a frequency multiplier for generating an internal clock signal having a frequency "n" times the frequency of the external clock signal. By providing the above-mentioned improvements, the conventional test equipment can be used to test high frequency memory devices.

    摘要翻译： 用于测试半导体存储器件的电路包括用于控制外部时钟信号的等待时间的等待时间控制器，用于在存储器件中产生列地址信号的内部列地址发生器和用于产生模式信号的模式寄存器。 用于测试半导体存储器件的电路还包括用于解码内部列地址发生器的输出地址信号的列地址解码器，用于读取或写入数据的存储单元，用于控制数据输入/输出的输入/输出控制单元 存储单元根据等待时间控制器的输出信号，数据输入缓冲器和数据输出缓冲器。 还提供了一种用于产生具有外部时钟信号频率“n”倍的内部时钟信号的倍频器。 通过提供上述改进，常规测试设备可用于测试高频存储器件。

    Wafer burn-in test circuit and method for testing a semiconductor memory device
    5.
    发明授权
    Wafer burn-in test circuit and method for testing a semiconductor memory device 有权
    晶圆老化测试电路和半导体存储器件测试方法

    公开(公告)号：US06266286B1

    公开(公告)日：2001-07-24

    申请号：US09457909

    申请日：1999-12-08

    申请人： Soo-In Cho ,  Jong-Hyun Choi

    发明人： Soo-In Cho ,  Jong-Hyun Choi

    IPC分类号： G11C700

    CPC分类号： G11C29/025 ,  G11C11/401 ,  G11C29/006 ,  G11C29/02 ,  G11C29/50

    摘要： A wafer burn-in test circuit of a semiconductor memory device having a plurality of memory cells arranged in a row/column matrix, is provided, including:a sub word line driver connected to first and second word line groups each connected to true cells and complement cells forming the memory cells, and responding to a predecoded low address; and first and second power lines respectively supplying power to the corresponding first and second power line groups by a switching operation of the sub word line driver, wherein a ground power source is applied to the first and second power lines during a normal operation, and the ground power source and a step-up power source are alternately applied to the first and second power lines during a wafer burn-in test operation.

    摘要翻译： 提供了具有以行/列矩阵排列的多个存储单元的半导体存储器件的晶片老化测试电路，包括：连接到每个连接到真实单元的第一和第二字线组的子字线驱动器，以及 形成存储器单元的补码单元，以及对预解码的低地址的响应; 以及分别通过子字线驱动器的切换操作向对应的第一和第二电力线组提供电力的第一和第二电力线，其中在正常操作期间将地电源施加到第一和第二电力线，并且 接地电源和升压电源在晶片老化测试操作期间交替施加到第一和第二电源线。

    Current-mode bidirectional input/output buffer
    6.
    发明授权
    Current-mode bidirectional input/output buffer 失效
    电流模式双向输入/输出缓冲器

    公开(公告)号：US6075384A

    公开(公告)日：2000-06-13

    申请号：US49739

    申请日：1998-03-27

    申请人： Jae-Yoon Sim ,  Hong-Joon Park ,  Soo-In Cho ,  Jung-Bae Lee

    发明人： Jae-Yoon Sim ,  Hong-Joon Park ,  Soo-In Cho ,  Jung-Bae Lee

    IPC分类号： H03K17/00 ,  H03K17/687 ,  H03K19/0175 ,  H03K19/0185

    CPC分类号： H03K19/018592

    摘要： A bidirectional input/output buffer operates in a current mode to increase the data transfer rate between devices connected by a bidirectional transmission line. The buffer includes an output current source for generating an output current responsive to a data output signal. The output current is combined with an output current indicative of a data input signal received from another device over a transmission line, thereby forming a mixed current signal. The data input signal is restored from the mixed signal by a restoring circuit that compares the mixed signal to a reference current that depends on the value of the data output signal. The restoring circuit includes a current mirror and a reference current source that generates a reference current in response to the data output signal. To provide additional performance, an embodiment of a bidirectional input/output buffer utilizes a switchless structure having two comparators that compare the mixed signal to two different reference signals, thereby generating two comparison signals. A selector circuit selects one of the two comparison signals as the restored data input signal responsive to the data output signal.

    摘要翻译： 双向输入/输出缓冲器以当前模式工作，以增加通过双向传输线连接的设备之间的数据传输速率。 缓冲器包括用于响应于数据输出信号产生输出电流的输出电流源。 输出电流与表示通过传输线从另一设备接收的数据输入信号的输出电流组合，从而形成混合电流信号。 数据输入信号通过将混合信号与取决于数据输出信号的值的参考电流进行比较的恢复电路从混合信号中恢复。 恢复电路包括响应于数据输出信号产生参考电流的电流镜和参考电流源。 为了提供额外的性能，双向输入/输出缓冲器的实施例利用具有两个比较器的无开关结构，其将混合信号与两个不同的参考信号进行比较，从而产生两个比较信号。 选择器电路根据数据输出信号选择两个比较信号中的一个作为恢复的数据输入信号。

    Boosting voltage generator of semiconductor memory device
    7.
    发明授权
    Boosting voltage generator of semiconductor memory device 失效
    升压型半导体存储器件的电压发生器

    公开(公告)号：US5659519A

    公开(公告)日：1997-08-19

    申请号：US585597

    申请日：1996-01-16

    申请人： Hyun-Seok Lee ,  Soo-In Cho

    发明人： Hyun-Seok Lee ,  Soo-In Cho

    IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C11/401 ,  G11C11/4074 ,  G11C11/408 ,  G11C29/00 ,  G11C29/04 ,  G11C11/40

    CPC分类号： G11C11/4085 ,  G11C11/4074 ,  G11C5/145

    摘要： A semiconductor memory device including at least two boosting voltage circuits which independently boost a supply voltage power level to a boosted voltage power level. A plurality of memory cell arrays each input the supply voltage power and store information therein. Driving circuits are connected to each of the memory cell arrays and supply the boosted voltage power to the memory cell arrays, the number of driving circuits preferably corresponding to the number of the boosting voltage circuits.

    摘要翻译： 一种半导体存储器件，包括至少两个升压电压电路，其独立地将电源电压功率电平升高到提升的电压功率电平。 多个存储单元阵列分别输入电源电压并存储信息。 驱动电路连接到每个存储单元阵列，并将提升的电压电力提供给存储单元阵列，驱动电路的数量优选地对应于升压电压电路的数量。

    Semiconductor memory device
    8.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5446697A

    公开(公告)日：1995-08-29

    申请号：US068547

    申请日：1993-05-28

    申请人： Seung-Moon Yoo ,  Ejaz ul Haq ,  Yun-Ho Choi ,  Soo-In Cho ,  Dae-Je Chin ,  Nam-Soo Kang ,  Seung-Hun Lee

    发明人： Seung-Moon Yoo ,  Ejaz ul Haq ,  Yun-Ho Choi ,  Soo-In Cho ,  Dae-Je Chin ,  Nam-Soo Kang ,  Seung-Hun Lee

    IPC分类号： G11C5/14 ,  H02M3/07 ,  G11C13/00

    CPC分类号： H02M3/07 ,  G11C5/145

    摘要： A semiconductor memory device stably operates over a wide range of the power supply voltage by including a power supply voltage level detector for generating detecting signals according to predetermined levels of the power supply voltage and an oscillator for generating a frequency-controlled oscillation pulse whose frequency is changeable according to the detecting signals. Thus, a boosting ratio of a boosting circuit, the refresh period of a refresh circuit and the substrate voltage of a substrate voltage generator can be adaptively changeable according to the variation of the power supply voltage.

    摘要翻译： 半导体存储器件通过包括用于根据电源电压的预定电平产生检测信号的电源电压电平检测器和用于产生频率为...的频率控制的振荡脉冲的振荡器，稳定地在宽范围的电源电压下工作 根据检测信号可变。 因此，升压电路的升压比，刷新电路的刷新周期和基板电压发生器的基板电压可以根据电源电压的变化自适应地变化。

    Semiconductor memory device having a plurality of row address strobe signals
    9.
    发明授权
    Semiconductor memory device having a plurality of row address strobe signals 失效
    具有多个行地址选通信号的半导体存储器件

    公开(公告)号：US5343438A

    公开(公告)日：1994-08-30

    申请号：US9475

    申请日：1993-02-01

    申请人： Yun-Ho Choi ,  Dae-Je Chin ,  Ejaz U. Haq ,  Soo-In Cho

    发明人： Yun-Ho Choi ,  Dae-Je Chin ,  Ejaz U. Haq ,  Soo-In Cho

    IPC分类号： G11C11/401 ,  G06F12/02 ,  G11C8/18 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/409 ,  G11C8/00

    CPC分类号： G11C8/18 ,  G11C11/4076

    摘要： The present invention relates to a semiconductor memory device, and more particularly to a dynamic random access memory for accomplishing high speed data access by supplying a plurality of row address strobe signals to a chip. A plurality of row address strobe signals are supplied to a plurality of pins, and each row address strobe signal is sequentially supplied with an active signal during a data access operation. Therefore, data in a plurality of memory cell arrays is accessed during one access cycle time. Thus, since a large number of random data are provided, the data access time decreases and the performance of a system can be greatly improved.

    摘要翻译： 本发明涉及一种半导体存储器件，更具体地说，涉及通过向芯片提供多个行地址选通信号来实现高速数据存取的动态随机存取存储器。 多个行地址选通信号被提供给多个引脚，并且每个行地址选通信号在数据访问操作期间被依次提供有效信号。 因此，在一个访问周期时间内访问多个存储单元阵列中的数据。 因此，由于提供大量随机数据，所以数据访问时间减少，并且可以大大提高系统的性能。