公开(公告)号：US5812466A

公开(公告)日：1998-09-22

申请号：US724798

申请日：1996-10-02

申请人： Jung-Hwa Lee ,  Jin-Man Han ,  Dong-Il Seo

发明人： Jung-Hwa Lee ,  Jin-Man Han ,  Dong-Il Seo

IPC分类号： G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/70

摘要： The present invention relates to a semiconductor memory device incorporating a column redundancy circuit using a decoded fuse. The column redundancy circuit is capable of designating a repaired address during a parallel test mode of memory operation when an address input is a "don't care," and it is particularly useful in a multiple input/output memory architecture which uses one column select per I/O line. The column redundancy circuit includes: transmitting means comprised of the data input/output lines for transmitting the data of the memory cell; column decoder and input/output control circuits connected to the transmitting means and decoding a column address input to input data; a circuit connected to the transmitting means and outputting a given signal to the column decoder and input/output control circuits in response to a plurality of output signals output from fuses and a signal for controlling the transmitting means; a plurality of decoded fuse circuits, the levels of which are determined by one fuse connected to the circuit; multiplexers for selectively transmitting data from one of the data input/output lines to a specific data bus line among a plurality of data bus lines; and a decoding circuit which receives the outputs of the decoded fuse circuits and generates a redundancy signal.

摘要翻译： 本发明涉及一种结合使用解码保险丝的列冗余电路的半导体存储器件。 当地址输入为“无关”时，列冗余电路能够在存储器操作的并行测试模式下指定修复的地址，并且在使用一列选择的多输入/输出存储器架构中特别有用 每个I / O线。 列冗余电路包括：发送装置，包括用于发送存储单元的数据的数据输入/输出线; 列解码器和连接到发送装置的输入/输出控制电路，并且将输入的列地址解码为输入数据; 连接到发送装置的电路，响应于从保险丝输出的多个输出信号和用于控制发送装置的信号，将给定信号输出到列解码器和输入/输出控制电路; 多个解码熔丝电路，其电平由连接到电路的一个熔丝确定; 多路复用器，用于选择性地将数据从数据输入/输出线之一发送到多条数据总线之间的特定数据总线; 以及解码电路，其接收解码的熔丝电路的输出并产生冗余信号。

公开(公告)号：US07462912B2

公开(公告)日：2008-12-09

申请号：US11361580

申请日：2006-02-24

申请人： Soon-Hong Ahn ,  Jung-Hwa Lee

发明人： Soon-Hong Ahn ,  Jung-Hwa Lee

IPC分类号： H01L29/76 ,  H01L29/00

CPC分类号： H01L27/0207 ,  H01L27/10894

摘要： Provided is a semiconductor memory device using a layout scheme where a bottom conductive layer in a peripheral circuit region, which is simultaneously formed with a self-align contact, is connected to one electrode of a power decoupling capacitor. Predetermined capacitors selected among a plurality of capacitors are connected to each other in parallel by using a conductive layer that is simultaneously formed with the self-align contact in a cell array region. Herein, the conductive layer and the self-align contact may be made of the same material. It is possible to embody the decoupling capacitor of a single stage cell type by connecting the conductive layer to a top interconnection layer. In addition, other embodiments implement the decoupling capacitor in a two-stage cell type by connecting a plurality of decoupling capacitors in series by means of the conductive layer in the peripheral circuit region.

摘要翻译： 提供了一种使用布局方案的半导体存储器件，其中同时形成有自对准接触的外围电路区域中的底部导电层连接到功率去耦电容器的一个电极。 通过使用与单元阵列区域中的自对准接触同时形成的导电层，并联地将多个电容器中选择的预定电容器并联连接。 这里，导电层和自对准接触可以由相同的材料制成。 通过将导电层连接到顶部互连层，可以体现单级电池类型的去耦电容器。 此外，其他实施例通过在外围电路区域中通过导电层连接多个解耦电容器来实现两级单元类型的去耦电容器。

公开(公告)号：US20070153612A1

公开(公告)日：2007-07-05

申请号：US11640857

申请日：2006-12-19

申请人： Jae-Young Lee ,  Hong-Jun Lee ,  Jung-Hwa Lee

发明人： Jae-Young Lee ,  Hong-Jun Lee ,  Jung-Hwa Lee

IPC分类号： G11C5/14

CPC分类号： G11C5/145

摘要： A circuit generates a boosted voltage in a semiconductor memory device, where the semiconductor memory device includes a memory cell array having a plurality of non-edge sub-arrays and at least one edge sub-array. The circuit includes a plurality of boosted voltage generators configured to generate a boosted voltage having different current driving capabilities to activate the non-edge sub-arrays and the edge sub-arrays and to supply the boosted voltage to the memory cell array.

摘要翻译： 电路在半导体存储器件中产生升压电压，其中半导体存储器件包括具有多个非边缘子阵列和至少一个边缘子阵列的存储单元阵列。 该电路包括多个升压电压发生器，其被配置为产生具有不同电流驱动能力的升压电压以激活非边缘子阵列和边缘子阵列，并将升压电压提供给存储单元阵列。

公开(公告)号：US20060289932A1

公开(公告)日：2006-12-28

申请号：US11361580

申请日：2006-02-24

申请人： Soon-Hong Ahn ,  Jung-Hwa Lee

发明人： Soon-Hong Ahn ,  Jung-Hwa Lee

IPC分类号： H01L29/76

CPC分类号： H01L27/0207 ,  H01L27/10894

摘要： Provided is a semiconductor memory device using a layout scheme where a bottom conductive layer in a peripheral circuit region, which is simultaneously formed with a self-align contact, is connected to one electrode of a power decoupling capacitor. Predetermined capacitors selected among a plurality of capacitors are connected to each other in parallel by using a conductive layer that is simultaneously formed with the self-align contact in a cell array region. Herein, the conductive layer and the self-align contact may be made of the same material. It is possible to embody the decoupling capacitor of a single stage cell type by connecting the conductive layer to a top interconnection layer. In addition, other embodiments implement the decoupling capacitor in a two-stage cell type by connecting a plurality of decoupling capacitors in series by means of the conductive layer in the peripheral circuit region.

摘要翻译： 提供了一种使用布局方案的半导体存储器件，其中同时形成有自对准接触的外围电路区域中的底部导电层连接到功率去耦电容器的一个电极。 通过使用与单元阵列区域中的自对准接触同时形成的导电层，并联地将多个电容器中选择的预定电容器并联连接。 这里，导电层和自对准接触可以由相同的材料制成。 通过将导电层连接到顶部互连层，可以体现单级电池类型的去耦电容器。 此外，其他实施例通过在外围电路区域中通过导电层连接多个解耦电容器来实现两级单元类型的去耦电容器。

公开(公告)号：US5657265A

公开(公告)日：1997-08-12

申请号：US673001

申请日：1996-07-01

申请人： Jei-Hwan Yoo ,  Jung-Hwa Lee

发明人： Jei-Hwan Yoo ,  Jung-Hwa Lee

IPC分类号： G11C11/41 ,  G11C7/10 ,  G11C11/401 ,  G11C11/4096 ,  H01L21/8242 ,  H01L27/108 ,  G11C5/06

CPC分类号： G11C7/10 ,  G11C11/4096

摘要： A semiconductor memory device includes at least four memory cell array blocks, each having an array of memory cells, row and column decoders for selecting a memory cell designated by a row and column address, an I/O line for inputting/outputting data of the memory cell array block, and an I/O driver connected to the I/O line for selectively driving data to/from a selected memory cell. A first data line transmits the data, being connected between the I/O driver of one memory cell array block and the I/O driver of another memory cell array block oppositely arranged with respect to a central portion of the semiconductor memory device. A second data line transmits the data by connecting the first data lines of at least two memory cell array blocks disposed adjacent to each other. A data sense amplifier, connected to the second data line, senses and amplifies the data, and a data output unit, connected to the data sense amplifier, outputs the amplified data to an external lead frame. Therefore, the present invention has an advantage in that a relatively small layout area in required and a relatively low amount of power is consumed.

摘要翻译： 半导体存储器件包括至少四个存储单元阵列块，每个存储单元阵列块具有存储单元阵列，用于选择由行和列地址指定的存储单元的行和列解码器，用于输入/输出数据的数据的I / O线 存储单元阵列块和连接到I / O线的I / O驱动器，用于选择性地将数据传送到所选择的存储单元。 第一数据线传送连接在一个存储单元阵列块的I / O驱动器和相对于半导体存储器件的中心部分相对布置的另一存储单元阵列块的I / O驱动器之间的数据。 第二数据线通过连接彼此相邻布置的至少两个存储单元阵列块的第一数据线来发送数据。 连接到第二数据线的数据读出放大器感测并放大数据，连接到数据读出放大器的数据输出单元将放大的数据输出到外部引线框。 因此，本发明的优点是消耗了所需的相对小的布局面积和相对低的功率。

公开(公告)号：US08295111B2

公开(公告)日：2012-10-23

申请号：US12894246

申请日：2010-09-30

申请人： Jae-Young Lee ,  Jung-Hwa Lee ,  Bong-Jin Kang

发明人： Jae-Young Lee ,  Jung-Hwa Lee ,  Bong-Jin Kang

IPC分类号： G11C7/00

CPC分类号： G11C11/4091 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/005

摘要： A semiconductor memory device comprises a substrate comprising a first cell array region, a first sense circuit region, a second sense circuit region, and a second cell array region that are arranged in order from a first side to a second side. First and second bit lines are coupled to a plurality of memory cells in the first cell array region, and first and second complementary bit lines are coupled to a plurality of memory cells in the second cell array region. A first column selector is formed in the first sense circuit region and is coupled to the first bit line and the first complementary bit line. A second column selector is formed in the second sense circuit region and is coupled to the second bit line and the second complementary bit line. The first column selector and the second column selector are formed directly adjacent to each other.

摘要翻译： 一种半导体存储器件，包括一个衬底，该衬底包括从第一侧到第二侧依次布置的第一单元阵列区，第一感测电路区，第二感测电路区和第二单元阵列区。 第一和第二位线耦合到第一单元阵列区域中的多个存储单元，并且第一和第二互补位线耦合到第二单元阵列区域中的多个存储单元。 第一列选择器形成在第一感测电路区域中，并且耦合到第一位线和第一互补位线。 第二列选择器形成在第二感测电路区域中，并且耦合到第二位线和第二互补位线。 第一列选择器和第二列选择器彼此直接相邻地形成。

公开(公告)号：US07573321B2

公开(公告)日：2009-08-11

申请号：US11858071

申请日：2007-09-19

申请人： Dong-Myung Eun ,  Jung-Hwa Lee

发明人： Dong-Myung Eun ,  Jung-Hwa Lee

IPC分类号： G05F1/10 ,  H03K3/01

CPC分类号： H02M3/07

摘要： A high voltage generator is provided. The high voltage generator may comprise a high voltage output node, a plurality of pumping stages, a plurality of charge transfer elements, and a field relieving unit. The plurality of pumping stages sequentially pump charges in response to a sequentially enabled plurality of pump signals and output the pumped charges, respectively. The plurality of charge transfer elements sequentially transfer the charges sequentially pumped by the plurality of pumping stages to the next pumping stage and transfer the charge of an output node of the last pumping stage to the high voltage output node. The field relieving unit reduces the voltage of the input terminal of at least one of the plurality of charge transfer elements. The high voltage generator reduces hot carrier injection in charge transfer transistors without decreasing pumping efficiency.

摘要翻译： 提供高压发生器。 高压发生器可以包括高压输出节点，多个泵送级，多个电荷转移元件和场释放单元。 多个泵送阶段响应于顺序启用的多个泵浦信号顺序地泵送电荷并分别输出泵送的电荷。 多个电荷转移元件顺序地将由多个泵送阶段泵浦的电荷转移到下一个泵送级，并将最后一个泵浦级的输出节点的电荷传送到高电压输出节点。 场释放单元降低多个电荷转移元件中的至少一个的输入端子的电压。 高压发生器减少电荷转移晶体管中的热载流子注入，而不会降低泵送效率。

公开(公告)号：US07542328B2

公开(公告)日：2009-06-02

申请号：US11777627

申请日：2007-07-13

申请人： Jung-Hwa Lee ,  Ji-Hyun Lee

发明人： Jung-Hwa Lee ,  Ji-Hyun Lee

IPC分类号： G11C11/24

CPC分类号： G11C29/02 ,  G11C11/401 ,  G11C29/025 ,  G11C29/12005 ,  G11C2029/1204

摘要： Provided is a bit line bridge detection method for selectively floating even-numbered or odd-numbered bit lines. The bit line bridge detection method simultaneously activates even-numbered sense amplifiers and odd-numbered sense amplifiers in response to a sense amplifier enable signal. The even-numbered sense amplifiers and the odd-numbered sense amplifiers are selectively disabled in response to a sense amplifier disable signal generated at a predetermined time after the sense amplifier enable signal is generated, and an even-numbered or odd-numbered sense amplifier selection signal which is stored in a mode register. As a result, the even-numbered bit lines and the odd-numbered bit lines are selectively floated. If data input to memory cells is inverted, a bit line bridge is detected.

摘要翻译： 提供了用于选择性地浮置偶数位或奇数位线的位线桥检测方法。 位线桥检测方法响应于读出放大器使能信号同时激活偶数读出放大器和奇数读出放大器。 响应于在产生读出放大器使能信号之后的预定时间产生的读出放大器禁止信号，选择性地禁止偶数读出放大器和奇数读出放大器，以及偶数或奇数读出放大器选择 信号存储在模式寄存器中。 结果，偶数位线和奇数位线被选择性浮动。 如果输入到存储单元的数据被反转，则检测位线桥。

公开(公告)号：US20070109904A1

公开(公告)日：2007-05-17

申请号：US11590313

申请日：2006-10-31

申请人： Sang-Pyo Hong ,  Jung-Hwa Lee

发明人： Sang-Pyo Hong ,  Jung-Hwa Lee

IPC分类号： G11C8/00

CPC分类号： G11C5/063 ,  G11C7/18 ,  G11C11/4097 ,  G11C2207/002 ,  H01L27/10885 ,  H01L27/10897

摘要： A memory core includes a first sub-memory array including a plurality of first memory cells, a second sub-memory array including a plurality of second memory cells, a bit line amplification circuit configured to amplify a voltage difference between the first bit line and the second bit line, and a column selection circuit including a first column selection transistor and a second column selection transistor, wherein the first and the second selection transistors share a drain and electrically couple the complementary bit line pair to a complementary local input/output line pair, respectively. As a result, the data error due to the distance mismatching can be reduced.

摘要翻译： 存储器芯包括包括多个第一存储器单元的第一子存储器阵列，包括多个第二存储单元的第二子存储器阵列，位线放大电路，被配置为放大第一位线和第二存储器单元之间的电压差 第二位线和包括第一列选择晶体管和第二列选择晶体管的列选择电路，其中第一和第二选择晶体管共享漏极，并将互补位线对电耦合到互补的本地输入/输出线对 ， 分别。 结果，可以减少由于距离不匹配引起的数据错误。

公开(公告)号：US20060163613A1

公开(公告)日：2006-07-27

申请号：US11336831

申请日：2006-01-23

申请人： Soo-Bong Chang ,  In-Chul Jeong ,  Jun-Hyung Kim ,  Seung-Min Oh ,  Jung-Hwa Lee

发明人： Soo-Bong Chang ,  In-Chul Jeong ,  Jun-Hyung Kim ,  Seung-Min Oh ,  Jung-Hwa Lee

IPC分类号： H01L27/10

CPC分类号： H01L27/0207 ,  H01L27/105 ,  H01L27/11898

摘要： A layout structure for sub word line drivers and method thereof. The example layout structure may include at least one N-channel transistor arrangement having a cross sectional width and a cross sectional length, the N-channel transistor arrangement oriented such that the cross sectional length extends along a first direction, the first direction oriented along a sub word line driver from a first sub array block to a second sub array block. The example method may arrange the at least one N-channel transistor between the first and second sub array blocks.

摘要翻译： 子字线驱动器的布局结构及其方法。 示例性布局结构可以包括具有横截面宽度和横截面长度的至少一个N沟道晶体管布置，N沟道晶体管布置方向使得横截面长度沿着第一方向延伸，第一方向沿着第一方向 子字线驱动器从第一子阵列块到第二子阵列块。 该示例性方法可以在第一和第二子阵列块之间布置至少一个N沟道晶体管。