公开(公告)号：US11435799B2

公开(公告)日：2022-09-06

申请号：US16988326

申请日：2020-08-07

Applicant: Kioxia Corporation

Inventor： Yoshihisa Kojima ,  Katsuhiko Ueki

IPC: G06F1/00 ,  G06F1/26 ,  G06F12/02

Abstract: In a memory system in an embodiment, in a case of normal operation, a control unit returns a write completion response upon completion of reception of write data from a host, and writes the write data into nonvolatile memory in a multiple values. In a case of unordinary power-off, changeover to operation using a backup battery is conducted and the control unit writes dirty data that is not completed in writing into the nonvolatile memory, into the nonvolatile memory with two values. When next boot, the control unit reads the dirty data from the nonvolatile memory into the volatile memory, and thereafter writes the dirty data into the nonvolatile memory in a multiple values.

公开(公告)号：US11347398B2

公开(公告)日：2022-05-31

申请号：US16913026

申请日：2020-06-26

Applicant: Kioxia Corporation

Inventor： Shizuka Endo ,  Riki Suzuki ,  Yoshihisa Kojima

IPC: G06F3/06

Abstract: According to one embodiment, a memory system includes a non-volatile memory and a controller. The memory includes a memory cell array. The controller is configured to control a transfer phase in which a command, an address, and first data are transferred to the memory, and a program phase in which the first data is programmed into the memory cell array by the memory after the transfer phase. The controller is configured to suspend the transfer phase after initiating the transfer phase before completion of the transfer phase, then read second data from the memory, and resume the transfer phase after reading of the second data is completed.

公开(公告)号：US11127476B2

公开(公告)日：2021-09-21

申请号：US16817371

申请日：2020-03-12

Applicant: Kioxia Corporation

Inventor： Kazutaka Takizawa ,  Yoshihisa Kojima ,  Sumio Kuroda ,  Masaaki Niijima

IPC: G11C16/34 ,  G11C29/44 ,  G11C16/14 ,  G11C16/12 ,  G11C16/26

Abstract: According to one embodiment, a memory system includes a first memory and a memory controller. The first memory is nonvolatile and includes a plurality of memory cell transistors, each of which stores data corresponding to a threshold voltage. The memory controller causes the first memory to execute a read operation to acquire data corresponding to the threshold voltage from the plurality of memory cell transistors on the basis of a result of comparison between the threshold voltage and a read voltage. The memory controller selects a first candidate value from among a plurality of candidate values for the read voltage in accordance with a degree of stress that affects the threshold voltage; and causes the first memory to execute the read operation using the first candidate value as the read voltage.

公开(公告)号：US11086718B2

公开(公告)日：2021-08-10

申请号：US16806131

申请日：2020-03-02

Applicant: KIOXIA CORPORATION

Inventor： Riki Suzuki ,  Toshikatsu Hida ,  Yoshihisa Kojima ,  Takehiko Amaki ,  Suguru Nishikawa

IPC: G06F11/00 ,  G06F11/10 ,  G06F3/06

Abstract: A memory system includes a nonvolatile memory, a buffer, and a controller. The buffer can temporarily store a plurality of data bits to be written to the nonvolatile memory. The controller can write the plurality of data bits, read from the buffer, to the nonvolatile memory; write a plurality of intermediate parity bits to the buffer, but not to the nonvolatile memory, wherein each of the plurality of intermediate parity bits is associated with an error correction process on each of the plurality of data bits; and write, to the nonvolatile memory, an accumulated parity bit that is an integration of the plurality of intermediate parity bits.

公开(公告)号：US12050812B2

公开(公告)日：2024-07-30

申请号：US18318078

申请日：2023-05-16

Applicant: Kioxia Corporation

Inventor： Suguru Nishikawa ,  Yoshihisa Kojima ,  Takehiko Amaki

IPC: G06F12/00 ,  G06F3/06 ,  G11C16/04 ,  G11C16/26 ,  G11C16/34 ,  G11C11/56

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0679 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3427 ,  G11C11/5642 ,  G11C11/5671

Abstract: A memory system includes a memory device having a memory cell array, and a controller. The memory cell array includes a plurality of first units and at least one second unit. The second unit includes the plurality of first units. The controller counts a first number of times of read operation for each of the plurality of first units, and, in response to the first number of times for one first unit among the plurality of first units reaching a first value, updates a second number of times for the second unit that includes the one first unit. In response to the second number of times reaching a second value, the controller determines whether to rewrite data stored in at least one of the first units included in the second unit.

公开(公告)号：US11941251B2

公开(公告)日：2024-03-26

申请号：US17982840

申请日：2022-11-08

Applicant: Kioxia Corporation

Inventor： Yoshihisa Kojima ,  Masanobu Shirakawa ,  Kiyotaka Iwasaki

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679

Abstract: According to one embodiment, there is provided a nonvolatile memory including a memory cell array, an input/output buffer, one or more intermediate buffers, and a control circuit. The memory cell array includes a plurality of pages. Each of the one or more intermediate buffers is electrically connected between the memory cell array and the input/output buffer. The control circuit is configured to store, in a first intermediate buffer, data read through sensing operation from a first page out of the plurality of pages in accordance with a first command that includes a sensing operation instruction and designation of the first intermediate buffer among the one or more intermediate buffers.

公开(公告)号：US11909415B2

公开(公告)日：2024-02-20

申请号：US17694057

申请日：2022-03-14

Applicant: Kioxia Corporation

Inventor： Masahiro Kiyooka ,  Riki Suzuki ,  Yoshihisa Kojima

IPC: H03M13/11 ,  G11C11/4074 ,  G11C11/4096 ,  H03M13/09

CPC classification number: H03M13/1125 ,  G11C11/4074 ,  G11C11/4096 ,  H03M13/098 ,  H03M13/1108

Abstract: A memory system according to an embodiment includes a nonvolatile memory and a memory controller. The nonvolatile memory includes a plurality of memory cells. The memory controller is configured to control the nonvolatile memory. In read operation for the memory cells, the memory controller is configured to: perform tracking including a plurality of reads in which a read voltage is shifted; determine a hard bit read voltage based on results of the tracking; calculate a soft bit read voltage based on the determined hard bit read voltage; perform soft bit read using the calculated soft bit read voltage; and perform a soft bit decoding process using a result of the soft bit read and a log-likelihood ratio table associated with the calculated soft bit read voltage.

公开(公告)号：US20230288973A1

公开(公告)日：2023-09-14

申请号：US18200453

申请日：2023-05-22

Applicant: Kioxia Corporation

Inventor： Yoshihisa Kojima ,  Katsuhiko Ueki

IPC: G06F1/26 ,  G06F12/02

CPC classification number: G06F1/263 ,  G06F12/0246 ,  G06F2212/205 ,  G06F2212/2028

Abstract: In a memory system in an embodiment, in a case of normal operation, a control unit returns a write completion response upon completion of reception of write data from a host, and writes the write data into nonvolatile memory in a multiple values. In a case of unordinary power-off, changeover to operation using a backup battery is conducted and the control unit writes dirty data that is not completed in writing into the nonvolatile memory, into the nonvolatile memory with two values. When next boot, the control unit reads the dirty data from the nonvolatile memory into the volatile memory, and thereafter writes the dirty data into the nonvolatile memory in a multiple values.

公开(公告)号：US11734112B2

公开(公告)日：2023-08-22

申请号：US17869881

申请日：2022-07-21

Applicant: Kioxia Corporation

Inventor： Takehiko Amaki ,  Toshikatsu Hida ,  Shunichi Igahara ,  Yoshihisa Kojima ,  Suguru Nishikawa

IPC: G11C29/00 ,  G06F11/10 ,  G06F12/0891 ,  G06F12/02 ,  G06F11/07

CPC classification number: G06F11/1068 ,  G06F11/073 ,  G06F11/1004 ,  G06F12/0246 ,  G06F12/0891

Abstract: According to one embodiment, a memory system includes a nonvolatile memory, a random access memory and a controller. When writing n−1 data portions of a first unit that are included in n−1 error correction code frames of a first size, respectively, in the nonvolatile memory, the controller generates a second error correction code that constitutes an error correction code frame of a second size together with the n−1 data portions of the first unit and a second data portion to be written into the nonvolatile memory by encoding the n−1 data portions of the first unit and the second data portion, and writes the second data portion and the second error correction code into the nonvolatile memory.

公开(公告)号：US20220365577A1

公开(公告)日：2022-11-17

申请号：US17878788

申请日：2022-08-01

Applicant: Kioxia Corporation

Inventor： Yoshihisa Kojima ,  Katsuhiko Ueki

IPC: G06F1/26 ,  G06F12/02

Abstract: In a memory system in an embodiment, in a case of normal operation, a control unit returns a write completion response upon completion of reception of write data from a host, and writes the write data into nonvolatile memory in a multiple values. In a case of unordinary power-off, changeover to operation using a backup battery is conducted and the control unit writes dirty data that is not completed in writing into the nonvolatile memory, into the nonvolatile memory with two values. When next boot, the control unit reads the dirty data from the nonvolatile memory into the volatile memory, and thereafter writes the dirty data into the nonvolatile memory in a multiple values.