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    Method and system for mixed mode wafer inspection
    31.
    发明授权
    Method and system for mixed mode wafer inspection 有权

    公开(公告)号：US11295438B2

    公开(公告)日：2022-04-05

    申请号：US16206691

    申请日：2018-11-30

    Applicant: KLA-Tencor Corporation

    Inventor： Jason Z. Lin ,  Allen Park ,  Ellis Chang ,  Richard Wallingford ,  Songnian Rong ,  Chetana Bhaskar

    IPC: G06T7/00

    Abstract: Mixed-mode includes receiving inspection results including one or more images of a selected region of the wafer, the one or more images include one or more wafer die including a set of repeating blocks, the set of repeating blocks a set of repeating cells. In addition, mixed-mode inspection includes adjusting a pixel size of the one or more images to map each cell, block and die to an integer number of pixels. Further, mixed-mode inspection includes comparing a first wafer die to a second wafer die to identify an occurrence of one or more defects in the first or second wafer die, comparing a first block to a second block to identify an occurrence of one or more defects in the first or second blocks and comparing a first cell to a second cell to identify an occurrence of one or more defects in the first or second cells.

    Using stochastic failure metrics in semiconductor manufacturing
    32.
    发明授权
    Using stochastic failure metrics in semiconductor manufacturing 有权

    公开(公告)号：US10818001B2

    公开(公告)日：2020-10-27

    申请号：US16241467

    申请日：2019-01-07

    Applicant: KLA-TENCOR CORPORATION

    Inventor： Wing-Shan Ribi Leung ,  Kaushik Sah ,  Allen Park ,  Andrew Cross

    IPC: G06T7/00 ,  G01N21/95

    Abstract: A stochastic calculation engine receives inputs from a semiconductor inspection tool or semiconductor review tool. The stochastic calculation engine determines abnormal locations and pattern variation from the inputs and determines stochastic failures from the inputs. An electronic data storage unit connected with the stochastic calculation engine can include a database with known stochastic behavior and known process metrology variations. The stochastic calculation engine can flag stochastic features, determine a failure rate, or determine fail probability.

    USING STOCHASTIC FAILURE METRICS IN SEMICONDUCTOR MANUFACTURING
    33.
    发明申请
    USING STOCHASTIC FAILURE METRICS IN SEMICONDUCTOR MANUFACTURING 审中-公开

    公开(公告)号：US20200082523A1

    公开(公告)日：2020-03-12

    申请号：US16241467

    申请日：2019-01-07

    Applicant: KLA-TENCOR CORPORATION

    Inventor： Wing-Shan Ribi Leung ,  Kaushik Sah ,  Allen Park ,  Andrew Cross

    IPC: G06T7/00 ,  G01N21/95

    Abstract: A stochastic calculation engine receives inputs from a semiconductor inspection tool or semiconductor review tool. The stochastic calculation engine determines abnormal locations and pattern variation from the inputs and determines stochastic failures from the inputs. An electronic data storage unit connected with the stochastic calculation engine can include a database with known stochastic behavior and known process metrology variations. The stochastic calculation engine can flag stochastic features, determine a failure rate, or determine fail probability.

    System, method and computer program product for systematic and stochastic characterization of pattern defects identified from a semiconductor wafer
    34.
    发明授权
    System, method and computer program product for systematic and stochastic characterization of pattern defects identified from a semiconductor wafer 有权

    公开(公告)号：US10262408B2

    公开(公告)日：2019-04-16

    申请号：US15683631

    申请日：2017-08-22

    Applicant: KLA-Tencor Corporation

    Inventor： Allen Park ,  Moshe Preil ,  Andrew James Cross

    IPC: G06T7/00 ,  G06K9/62

    Abstract: A system, method, and computer program product are provided for systematic and stochastic characterization of pattern defects identified from a fabricated component. In use, a plurality of pattern defects detected from a fabricated component are identified. Additionally, attributes of each of the pattern defects are analyzed, based on predefined criteria. Further, a first set of pattern defects of the plurality of pattern defects are determined, from the analysis, to be systematic pattern defects, and a second set of pattern defects of the plurality of pattern defects are determined, from the analysis, to be stochastic pattern defects. Moreover, a first action is performed for the determined systematic pattern defects and a second action is performed for the determined stochastic pattern defects.

    Method and system for mixed mode wafer inspection
    35.
    发明授权
    Method and system for mixed mode wafer inspection 有权

    公开(公告)号：US10192303B2

    公开(公告)日：2019-01-29

    申请号：US14076350

    申请日：2013-11-11

    Applicant: KLA-Tencor Corporation

    Inventor： Jason Z. Lin ,  Allen Park ,  Ellis Chang ,  Richard Wallingford ,  Songnian Rong ,  Chetana Bhaskar

    IPC: G06K9/00 ,  G06T7/00

    Abstract: Mixed-mode includes receiving inspection results including one or more images of a selected region of the wafer, the one or more images include one or more wafer die including a set of repeating blocks, the set of repeating blocks a set of repeating cells. In addition, mixed-mode inspection includes adjusting a pixel size of the one or more images to map each cell, block and die to an integer number of pixels. Further, mixed-mode inspection includes comparing a first wafer die to a second wafer die to identify an occurrence of one or more defects in the first or second wafer die, comparing a first block to a second block to identify an occurrence of one or more defects in the first or second blocks and comparing a first cell to a second cell to identify an occurrence of one or more defects in the first or second cells.

    Self Directed Metrology and Pattern Classification
    36.
    发明申请
    Self Directed Metrology and Pattern Classification 审中-公开
    自导计量和模式分类

    公开(公告)号：US20160372303A1

    公开(公告)日：2016-12-22

    申请号：US15247774

    申请日：2016-08-25

    Applicant: KLA-Tencor Corporation

    Inventor： Allen Park ,  Ajay Gupta ,  Jan Lauber

    IPC: H01J37/22 ,  G06K9/62 ,  G06T7/00

    CPC classification number: H01J37/222 ,  G01N21/956 ,  G01N2021/8883 ,  G03F7/70625 ,  G06K9/6267 ,  G06T7/0004 ,  G06T7/11 ,  G06T2207/30148 ,  H01J2237/2817 ,  H01L22/12 ,  H01L22/20

    Abstract: Methods and systems for determining parameter(s) of a process to be performed on a specimen are provided. One system includes one or more computer subsystems configured for determining an area of a defect detected on a specimen. The computer subsystem(s) are also configured for correlating the area of the defect with information for a design for the specimen and determining a spatial relationship between the area of the defect and the information for the design based on results of the correlating. In addition, the computer subsystem(s) are configured for automatically generating a region of interest to be measured during a process performed for the specimen with a measurement subsystem based on the spatial relationship.

    Abstract translation: 提供了用于确定要在样本上执行的过程的参数的方法和系统。 一个系统包括被配置用于确定在样本上检测到的缺陷区域的一个或多个计算机子系统。 计算机子系统还被配置为将缺陷的区域与用于样本的设计的信息相关联，并且基于相关的结果确定缺陷的区域与设计的信息之间的空间关系。 此外，计算机子系统被配置为在基于空间关系的测量子系统对于具有样本的处理过程中自动生成要测量的感兴趣区域。

    Detecting IC Reliability Defects
    39.
    发明申请
    Detecting IC Reliability Defects 审中-公开
    检测IC可靠性缺陷

    公开(公告)号：US20150120220A1

    公开(公告)日：2015-04-30

    申请号：US14512446

    申请日：2014-10-12

    Applicant: KLA-Tencor Corporation

    Inventor： Joanne Wu ,  Ellis Chang ,  Lisheng Gao ,  Satya Kurada ,  Allen Park ,  Raghav Babulnath

    IPC: G01N21/95

    CPC classification number: H01L22/12 ,  G01N21/8851 ,  G01N21/956 ,  H01L22/14 ,  H01L22/20

    Abstract: Methods and systems for detecting reliability defects on a wafer are provided. One method includes acquiring output for a wafer generated by an inspection system. The method also includes determining one or more geometric characteristics of one or more patterned features formed on the wafer based on the output. In addition, the method includes identifying which of the one or more patterned features will cause one or more reliability defects in a device being formed on the wafer based on the determined one or more characteristics.

    Abstract translation: 提供了用于检测晶片上的可靠性缺陷的方法和系统。 一种方法包括获取由检查系统产生的晶片的输出。 该方法还包括基于输出来确定在晶片上形成的一个或多个图案特征的一个或多个几何特征。 此外，该方法包括基于所确定的一个或多个特性来识别一个或多个图案化特征中的哪一个将导致在晶片上形成的器件中的一个或多个可靠性缺陷。

    Method and System for Mixed Mode Wafer Inspection
    40.
    发明申请
    Method and System for Mixed Mode Wafer Inspection 审中-公开
    混合晶圆检验方法与系统

    公开(公告)号：US20140153814A1

    公开(公告)日：2014-06-05

    申请号：US14076350

    申请日：2013-11-11

    Applicant: KLA-Tencor Corporation

    Inventor： Jason Z. Lin ,  Allen Park ,  Ellis Chang ,  Richard Wallingford ,  Songnian Rong ,  Chetana Bhaskar

    IPC: G06T7/00

    CPC classification number: G06T7/001 ,  G06T2207/30148

    Abstract: Mixed-mode includes receiving inspection results including one or more images of a selected region of the wafer, the one or more images include one or more wafer die including a set of repeating blocks, the set of repeating blocks a set of repeating cells. In addition, mixed-mode inspection includes adjusting a pixel size of the one or more images to map each cell, block and die to an integer number of pixels. Further, mixed-mode inspection includes comparing a first wafer die to a second wafer die to identify an occurrence of one or more defects in the first or second wafer die, comparing a first block to a second block to identify an occurrence of one or more defects in the first or second blocks and comparing a first cell to a second cell to identify an occurrence of one or more defects in the first or second cells.

    Abstract translation: 混合模式包括接收包括晶片的选定区域的一个或多个图像的检查结果，一个或多个图像包括一个或多个晶片管芯，其包括一组重复块，该组重复块是一组重复的单元。 此外，混合模式检查包括调整一个或多个图像的像素尺寸以将每个单元映射到块，并将其死亡到整数个像素。 此外，混合模式检查包括将第一晶片管芯与第二晶片管芯进行比较，以识别第一或第二晶片管芯中的一个或多个缺陷的发生，将第一块与第二块进行比较以识别一个或多个 第一或第二块中的缺陷，并且将第一细胞与第二细胞进行比较以识别第一或第二细胞中的一个或多个缺陷的发生。

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