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31.发明申请公开(公告)号：US20150298282A1
公开(公告)日：2015-10-22
申请号：US14313733
申请日：2014-06-24
Applicant: KLA-Tencor Corporation
Inventor： Pradeep Vukkadala , Jaydeep Sinha
IPC: B24B37/005 , G01B5/28 , G03F7/20 , B24B49/00
CPC classification number: B24B37/005 , B24B49/00 , G01B21/00 , G01B2210/48 , G03F7/705 , G03F9/7026 , G06N7/00 , G06N20/00
Abstract: Wafer geometry measurement tools and methods for providing improved wafer geometry measurements are disclosed. Wafer front side, backside and flatness measurements are taken into consideration for semiconductor process control. The measurement tools and methods in accordance with embodiments of the present disclosure are suitable for handling any types of wafers, including patterned wafers, without the shortcomings of conventional metrology systems.
Abstract translation: 公开了用于提供改进的晶片几何测量的晶片几何测量工具和方法。 考虑到半导体工艺控制的晶片正面，背面和平坦度测量。 根据本公开的实施例的测量工具和方法适用于处理任何类型的晶片，包括图案化晶片，而没有传统测量系统的缺点。
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32.发明申请Using Wafer Geometry to Improve Scanner Correction Effectiveness for Overlay Control 有权使用晶片几何来提高覆盖控制的扫描仪校正有效性公开(公告)号：US20150212429A1
公开(公告)日：2015-07-30
申请号：US14683880
申请日：2015-04-10
Applicant: KLA-Tencor Corporation
Inventor： Craig MacNaughton , Sathish Veeraraghavan , Pradeep Vukkadala , Jaydeep Sinha , Amir Azordegan
IPC: G03F7/20 , H01J37/317
CPC classification number: G03F7/70616 , G03F7/70633 , G03F7/70783 , G03F9/7003 , H01J37/28 , H01J37/304 , H01J37/3172 , H01J37/3174 , H01J2237/221 , H01J2237/2814 , H01J2237/30472 , H01J2237/30483 , H01J2237/31701
Abstract: Systems and methods for providing improved scanner corrections are disclosed. Scanner corrections provided in accordance with the present disclosure may be referred to as wafer geometry aware scanner corrections. More specifically, wafer geometry and/or wafer shape signature information are utilized to improve scanner corrections. By removing the wafer geometry as one of the error sources that may affect the overlay accuracy, better scanner corrections can be obtained because one less contributing factor needs to be modeled.
Abstract translation: 公开了用于提供改进的扫描仪校正的系统和方法。 根据本公开提供的扫描仪校正可以被称为晶片几何感知扫描仪校正。 更具体地，利用晶片几何形状和/或晶片形状签名信息来改进扫描器校正。 通过将晶片几何作为可能影响覆盖精度的错误源之一，可以获得更好的扫描仪校正，因为需要对一个较少的因素进行建模。
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公开(公告)号：US10788759B2
公开(公告)日：2020-09-29
申请号：US16049266
申请日：2018-07-30
Applicant: KLA-Tencor Corporation
Inventor： Bin-Ming Benjamin Tsai , Oreste Donzella , Pradeep Vukkadala , Jaydeep Sinha
Abstract: Prediction based systems and methods for optimizing wafer chucking and lithography control are disclosed. Distortions predicted to occur when a wafer is chucked by a chucking device are calculated and are utilized to control chucking parameters of the chucking device. Chucking parameters may include chucking pressures and chucking sequences. In addition, predicted distortions may also be utilized to facilitate application of anticipatory corrections. Controlling chucking parameters and/or applying anticipatory corrections help reducing or minimizing overlay errors.
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Patent Agency Ranking
公开(公告)号：US10576603B2
公开(公告)日：2020-03-03
申请号：US14313733
申请日：2014-06-24
Applicant: KLA-Tencor Corporation
Inventor： Pradeep Vukkadala , Jaydeep Sinha
Abstract: Wafer geometry measurement tools and methods for providing improved wafer geometry measurements are disclosed. Wafer front side, backside and flatness measurements are taken into consideration for semiconductor process control. The measurement tools and methods in accordance with embodiments of the present disclosure are suitable for handling any types of wafers, including patterned wafers, without the shortcomings of conventional metrology systems.
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公开(公告)号：US20180364579A1
公开(公告)日：2018-12-20
申请号：US16049266
申请日：2018-07-30
Applicant: KLA-Tencor Corporation
Inventor： Bin-Ming Benjamin Tsai , Oreste Donzella , Pradeep Vukkadala , Jaydeep Sinha
IPC: G03F7/20
CPC classification number: G03F7/707 , G03F7/70783
Abstract: Prediction based systems and methods for optimizing wafer chucking and lithography control are disclosed. Distortions predicted to occur when a wafer is chucked by a chucking device are calculated and are utilized to control chucking parameters of the chucking device. Chucking parameters may include chucking pressures and chucking sequences. In addition, predicted distortions may also be utilized to facilitate application of anticipatory corrections. Controlling chucking parameters and/or applying anticipatory corrections help reducing or minimizing overlay errors.
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36.发明授权Predicting and controlling critical dimension issues and pattern defectivity in wafers using interferometry 有权使用干涉测量预测和控制晶片中的关键尺寸问题和图案缺陷公开(公告)号：US09558545B2
公开(公告)日：2017-01-31
申请号：US14730997
申请日：2015-06-04
Applicant: KLA-Tencor Corporation
Inventor： Pradeep Vukkadala , Sathish Veeraraghavan , Soham Dey , Jaydeep Sinha
CPC classification number: G06T7/0004 , G06K9/6201 , G06T7/001 , G06T2207/10004 , G06T2207/30148 , H01L22/12 , H01L22/20
Abstract: Systems and methods for predicting and controlling pattern quality data (e.g., critical dimension and/or pattern defectivity) in patterned wafers using patterned wafer geometry (PWG) measurements are disclosed. Correlations between PWG measurements and pattern quality data measurements may be established, and the established correlations may be utilized to provide pattern quality data predictions for a given wafer based on geometry measurements obtained for the give wafer. The predictions produced may be provided to a lithography tool, which may utilize the predictions to correct focus and/or title errors that may occur during the lithography process.
Abstract translation: 公开了使用图案化晶片几何（PWG）测量在图案化晶片中预测和控制图案质量数据（例如临界尺寸和/或图案缺陷率）的系统和方法。 可以建立PWG测量和模式质量数据测量之间的相关性，并且可以利用所建立的相关性来基于为给定晶片获得的几何测量来为给定晶片提供图案质量数据预测。 可以将所产生的预测提供给光刻工具，光刻工具可以利用预测来校正可能在光刻工艺期间发生的焦点和/或标题误差。
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37.发明申请Enhanced Patterned Wafer Geometry Measurements Based Design Improvements for Optimal Integrated Chip Fabrication Performance 有权基于增强图案化晶圆几何测量的设计改进，优化集成芯片制造性能公开(公告)号：US20160071260A1
公开(公告)日：2016-03-10
申请号：US14520998
申请日：2014-10-22
Applicant: KLA-Tencor Corporation
Inventor： Amir Azordegan , Pradeep Vukkadala , Craig MacNaughton , Jaydeep Sinha
CPC classification number: G01N21/9501 , G01B11/24 , G01N21/956 , G06T3/4069
Abstract: Methods and systems enabling ultra-high resolution topography measurements of patterned wafers are disclosed. Measurements obtained utilizing the ultra-high resolution metrology may be utilized to improve wafer metrology measurement accuracies. Additionally, measurements obtained utilizing the ultra-high resolution metrology may also be utilized to provide feedback and/or calibration control to improve fabrication and design of wafers.
Abstract translation: 公开了能够对图案化晶片进行超高分辨率地形测量的方法和系统。 可以利用超高分辨率测量获得的测量来提高晶片度量测量精度。 此外，利用超高分辨率度量获得的测量结果也可用于提供反馈和/或校准控制以改善晶片的制造和设计。
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38.发明申请Process-Induced Distortion Prediction and Feedforward and Feedback Correction of Overlay Errors 审中-公开过程诱导的失真预测和覆盖误差的前馈和反馈校正公开(公告)号：US20150120216A1
公开(公告)日：2015-04-30
申请号：US14490408
申请日：2014-09-18
Applicant: KLA-Tencor Corporation
Inventor： Pradeep Vukkadala , Haiguang Chen , Jaydeep Sinha , Sathish Veeraraghavan
CPC classification number: G01N19/08 , C23C14/54 , G01L1/00 , G01L5/0047 , G03F7/705 , G03F7/70633 , G03F7/70783 , H01L22/12 , H01L22/20
Abstract: Systems and methods for prediction and measurement of overlay errors are disclosed. Process-induced overlay errors may be predicted or measured utilizing film force based computational mechanics models. More specifically, information with respect to the distribution of film force is provided to a finite element (FE) model to provide more accurate point-by-point predictions in cases where complex stress patterns are present. Enhanced prediction and measurement of wafer geometry induced overlay errors are also disclosed.
Abstract translation: 公开了用于预测和测量重叠误差的系统和方法。 可以使用基于薄膜力的计算力学模型来预测或测量过程引起的重叠误差。 更具体地，关于膜力的分布的信息被提供给有限元（FE）模型，以在存在复应力模式的情况下提供更准确的逐点预测。 还公开了晶片几何感应重叠误差的增强预测和测量。
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