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    SELF-ALIGNED CONTACT STRUCTURE IN A SEMICONDUCTOR DEVICE
    32.
    发明申请
    SELF-ALIGNED CONTACT STRUCTURE IN A SEMICONDUCTOR DEVICE 审中-公开
    半导体器件中的自对准接触结构

    公开(公告)号：US20090194825A1

    公开(公告)日：2009-08-06

    申请号：US12176469

    申请日：2008-07-21

    申请人： Thomas Werner ,  Frank Feustel ,  Kai Frohberg

    发明人： Thomas Werner ,  Frank Feustel ,  Kai Frohberg

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L21/76897 ,  H01L21/28123 ,  H01L21/28518 ,  H01L21/76232

    摘要： By forming an isolation structure that extends above the height level defined by the semiconductor material of an active region, respective recesses may be defined in combination with gate electrode structures of the completion of basic transistor structures. These recesses may be subsequently filled with an appropriate contact material, thereby forming large area contacts in a self-aligned manner without requiring deposition and patterning of an interlayer dielectric material. Thereafter, the first metallization layer may be formed, for instance, on the basis of well-established techniques wherein the metal lines may connect directly to respective “large area” contact elements.

    摘要翻译： 通过形成在由有源区的半导体材料限定的高度水平之上延伸的隔离结构，相应的凹槽可以与完成基本晶体管结构的栅电极结构相结合。 这些凹部可以随后用适当的接触材料填充，从而以自对准的方式形成大面积的接触，而不需要层间绝缘材料的沉积和图案化。 此后，例如，可以基于公知的技术形成第一金属化层，其中金属线可以直接连接到相应的“大面积”接触元件。

    Method of forming an etch indicator layer for reducing etch non-uniformities
    34.
    发明授权
    Method of forming an etch indicator layer for reducing etch non-uniformities 有权
    形成蚀刻指示剂层以减少蚀刻非均匀性的方法

    公开(公告)号：US07462563B2

    公开(公告)日：2008-12-09

    申请号：US11688280

    申请日：2007-03-20

    申请人： Frank Feustel ,  Thomas Werner ,  Kai Frohberg

    发明人： Frank Feustel ,  Thomas Werner ,  Kai Frohberg

    IPC分类号： H01L21/311

    CPC分类号： H01L21/31144 ,  H01L21/26506 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76825 ,  H01L22/26 ,  H01L29/66636 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

    摘要： By incorporating an etch control material after the formation of a material layer to be patterned, an appropriate material having a highly distinctive radiation wavelength may be used for generating a distinctive endpoint detection signal during an etch process. Advantageously, the material may be incorporated by ion implantation which provides reduced non-uniformity compared to etch non-uniformities, while the implantation process provides the potential for introducing even very “exotic” implantation species. In some embodiments, the substrate-to-substrate uniformity of the patterning of dual damascene structures may be increased.

    摘要翻译： 通过在形成待图案化的材料层之后并入蚀刻控制材料，可以使用具有高度显着的辐射波长的适当材料来在蚀刻工艺期间产生独特的端点检测信号。 有利地，该材料可以通过离子注入并入，与蚀刻非均匀性相比，其提供了降低的不均匀性，而植入工艺提供了引入甚至非常“异乎寻常”的植入物种的潜力。 在一些实施例中，可以增加双镶嵌结构的图案化的基板到基板的均匀性。

    METHOD FOR THE PROTECTION OF METAL LAYERS AGAINST EXTERNAL CONTAMINATION
    35.
    发明申请
    METHOD FOR THE PROTECTION OF METAL LAYERS AGAINST EXTERNAL CONTAMINATION 审中-公开
    保护外部污染金属层的方法

    公开(公告)号：US20080160762A1

    公开(公告)日：2008-07-03

    申请号：US11778291

    申请日：2007-07-16

    申请人： Frank Feustel ,  Thomas Werner ,  Kai Frohberg

    发明人： Frank Feustel ,  Thomas Werner ,  Kai Frohberg

    IPC分类号： H01L21/443

    CPC分类号： H01L21/76843 ,  H01L21/76856 ,  H01L21/76861 ,  H01L21/76873

    摘要： In order to avoid the contamination of a seed layer, which is typically highly reactive with the external atmosphere, during the formation of interconnect structures in a semiconductor device, a protective layer is formed. The protective layer may be comprised of oxide formed in an oxidizing ambient prior to transporting the semiconductor device to a subsequent process tool.

    摘要翻译： 为了避免在半导体器件形成互连结构期间通常与外部大气反应的种子层的污染，形成保护层。 在将半导体器件传送到随后的处理工具之前，保护层可以由在氧化环境中形成的氧化物构成。

    TECHNIQUE FOR FORMING AN ISOLATION TRENCH AS A STRESS SOURCE FOR STRAIN ENGINEERING
    38.
    发明申请
    TECHNIQUE FOR FORMING AN ISOLATION TRENCH AS A STRESS SOURCE FOR STRAIN ENGINEERING 有权
    用于形成分离条件的技术作为应变工程的应力源

    公开(公告)号：US20070155121A1

    公开(公告)日：2007-07-05

    申请号：US11534726

    申请日：2006-09-25

    申请人： Kai Frohberg ,  Patrick Press ,  Thomas Werner

    发明人： Kai Frohberg ,  Patrick Press ,  Thomas Werner

    IPC分类号： H01L21/76

    CPC分类号： H01L21/84 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203

    摘要： By forming a non-oxidizable liner in an isolation trench and selectively modifying the liner within the isolation trench, the stress characteristics of the isolation trench may be adjusted. In one embodiment, a high compressive stress may be obtained by treating the liner with an ion bombardment and subsequently exposing the device to an oxidizing ambient at elevated temperatures, thereby incorporating silicon dioxide into the non-oxidizable material. Hence, an increased compressive stress may be generated within the non-oxidizable layer.

    摘要翻译： 通过在隔离沟槽中形成不可氧化的衬垫并且选择性地修改隔离沟槽内的衬垫，可以调节隔离沟槽的应力特性。 在一个实施例中，可以通过用离子轰击处理衬垫并随后在升高的温度下将器件暴露于氧化环境，从而将二氧化硅掺入到不可氧化的材料中，可获得高的压缩应力。 因此，可以在非可氧化层内产生增加的压应力。

    Metallization system of a semiconductor device comprising extra-tapered transition vias
    39.
    发明授权
    Metallization system of a semiconductor device comprising extra-tapered transition vias 有权
    包括超锥形过渡通孔的半导体器件的金属化系统

    公开(公告)号：US08835303B2

    公开(公告)日：2014-09-16

    申请号：US12634216

    申请日：2009-12-09

    申请人： Frank Feustel ,  Thomas Werner ,  Kai Frohberg

    发明人： Frank Feustel ,  Thomas Werner ,  Kai Frohberg

    IPC分类号： H01L21/4763 ,  H01L21/768

    CPC分类号： H01L21/76807 ,  H01L21/76804 ,  H01L21/76813

    摘要： In a metallization system of a semiconductor device, a transition via may be provided with an increased degree of tapering by modifying a corresponding etch sequence. For example, the resist mask for forming the via opening may be eroded once or several times in order to increase the lateral size of the corresponding mask opening. Due to the pronounced degree of tapering, enhanced deposition conditions may be accomplished during the subsequent electrochemical deposition process for commonly filling the via opening and a wide trench connected thereto.

    摘要翻译： 在半导体器件的金属化系统中，可以通过修改相应的蚀刻顺序来提供过渡通孔的增加的锥度。 例如，为了增加对应的掩模开口的横向尺寸，用于形成通路孔的抗蚀剂掩模可以被腐蚀一次或几次。 由于显着的渐缩度，在随后的电化学沉积过程中可以实现增强的沉积条件，用于通常填充通孔开口和与其连接的宽沟槽。