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    Superior fill conditions in a replacement gate approach by using a tensile stressed overlayer
    5.
    发明授权
    Superior fill conditions in a replacement gate approach by using a tensile stressed overlayer 有权
    通过使用拉伸应力覆盖层，更换浇口方法的优异填充条件

    公开(公告)号：US08198147B2

    公开(公告)日：2012-06-12

    申请号：US12854264

    申请日：2010-08-11

    申请人： Frank Feustel ,  Kai Frohberg ,  Thomas Werner

    发明人： Frank Feustel ,  Kai Frohberg ,  Thomas Werner

    IPC分类号： H01L21/00

    CPC分类号： H01L21/823807 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/7843

    摘要： In a replacement gate approach for forming high-k metal gate electrodes in semiconductor devices, a tapered configuration of the gate openings may be accomplished by using a tensile stressed dielectric material provided laterally adjacent to the gate electrode structure. Consequently, superior deposition conditions may be achieved while the tensile stress component may be efficiently used for the strain engineering in one type of transistor. Furthermore, an additional compressively stressed dielectric material may be applied after providing the replacement gate electrode structures.

    摘要翻译： 在用于在半导体器件中形成高k金属栅电极的替代栅极方法中，栅极开口的锥形配置可以通过使用横向邻近栅电极结构设置的拉应力电介质材料来实现。 因此，可以实现优异的沉积条件，同时可以有效地将拉伸应力分量用于一种类型的晶体管中的应变工程。 此外，可以在提供替换栅电极结构之后施加附加的压缩应力介电材料。

    USING A CAP LAYER IN METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES AS A CMP AND ETCH STOP LAYER
    9.
    发明申请
    USING A CAP LAYER IN METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES AS A CMP AND ETCH STOP LAYER 审中-公开
    在作为CMP和蚀刻停止层的半导体器件的金属化系统中使用CAP层

    公开(公告)号：US20100052181A1

    公开(公告)日：2010-03-04

    申请号：US12483571

    申请日：2009-06-12

    申请人： Thomas Werner ,  Kai Frohberg ,  Frank Feustel

    发明人： Thomas Werner ,  Kai Frohberg ,  Frank Feustel

    IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/528

    CPC分类号： H01L21/76829 ,  H01L21/76832 ,  H01L21/76849 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： During the manufacture of advanced metallization systems, a dielectric cap layer formed on a sensitive dielectric material may be partially maintained during a CMP process for removing excess metal, thereby avoiding the necessity for depositing a dedicated etch stop material, as may be required in conventional approaches when substantially completely consuming the dielectric cap material during the CMP process. Hence, reduced process complexity and/or enhanced flexibility may be accomplished in combination with increased integrity of the low-k dielectric material.

    摘要翻译： 在制造先进的金属化系统期间，在CMP工艺中可以部分保持形成在敏感电介质材料上的电介质盖层，以去除多余的金属，从而避免沉积专用蚀刻停止材料的必要性，如常规方法中所需要的 当在CMP工艺期间基本上完全消耗电介质盖材料时。 因此，降低的工艺复杂性和/或增强的柔性可以与低k介电材料的增加的完整性相结合来实现。

    METHOD FOR REDUCING METAL IRREGULARITIES IN ADVANCED METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES
    10.
    发明申请
    METHOD FOR REDUCING METAL IRREGULARITIES IN ADVANCED METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES 审中-公开
    降低半导体器件高级金属化系统金属不正常性的方法

    公开(公告)号：US20090298279A1

    公开(公告)日：2009-12-03

    申请号：US12394248

    申请日：2009-02-27

    申请人： Frank Feustel ,  Kai Frohberg ,  Thomas Werner

    发明人： Frank Feustel ,  Kai Frohberg ,  Thomas Werner

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76814 ,  H01L21/02063 ,  H01L21/67745 ,  H01L21/76843 ,  H01L21/76877

    摘要： In a manufacturing sequence for forming metallization levels of semiconductor devices, out-gassing of volatile components after an etch process may be initiated immediately after the etch process, thereby reducing the probability of creating contaminants in other substrates and transport carriers during transport activities. Consequently, the defect rate of deposition-related irregularities in the metallization level may be reduced.

    摘要翻译： 在用于形成半导体器件的金属化水平的制造顺序中，可以在蚀刻工艺之后立即开始蚀刻工艺之后的挥发性组分的排气，从而降低在运输活动期间在其它基底和运输载体中产生污染物的可能性。 因此，可以降低金属化水平的沉积相关不规则性的缺陷率。