公开(公告)号：US5834851A

公开(公告)日：1998-11-10

申请号：US460641

申请日：1995-06-02

申请人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

发明人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

IPC分类号： H01L27/11

CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903 ,  Y10S257/904

摘要： Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially. The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines.The source line is formed of a conductive layer identical to that of the word line. The individual data lines of the complementary data line are formed of an identical conductive layer which is different from that of the word line and the source line. The identical conductive layer between the word line and source line and the complementary data line is formed with two word lines: a main word line extended in the first direction identical to that of the word line and source line and used by adopting the divided word line system: and a sub-word line used by adopting the double word line system.

摘要翻译： 这里公开了一种半导体集成电路器件，其包括具有其存储单元的SRAM，SRAM由通过字线控制的转移MISFET和驱动MISFET构成。 驱动MISFET的栅电极和存储单元的转移MISFET的栅电极和字线分别由不同的导电层形成。 驱动MISFET和转移MISFET分别布置成在栅极长度方向上彼此交叉。 字线在驱动MISFET的栅电极的栅极长度方向上延伸，并且部分地与驱动MISFET的栅电极交叉。 存储器单元的两个转移MISFET的各自的栅极电极与彼此间隔开并沿相同方向延伸的两个相应字线连接。 由两个字线限定的区域配置有两个驱动MISFET和源极线。 源极线由与字线的导电层相同的导电层形成。 互补数据线的各个数据线由与字线和源极线不同的导电层形成。 字线和源极线与互补数据线之间的相同的导电层由两条字线形成：主字线在第一方向上延伸，与字线和源极线相同，并通过采用分割字线 系统：采用双字线系统使用的子字线。

公开(公告)号：US5122857A

公开(公告)日：1992-06-16

申请号：US638768

申请日：1991-01-08

申请人： Shuji Ikeda ,  Katsuro Sasaki ,  Kouichi Nagasawa ,  Satoshi Meguro

发明人： Shuji Ikeda ,  Katsuro Sasaki ,  Kouichi Nagasawa ,  Satoshi Meguro

IPC分类号： H01L21/768 ,  G11C11/41 ,  H01L21/8244 ,  H01L23/522 ,  H01L27/10 ,  H01L27/11

CPC分类号： H01L27/11 ,  H01L27/1112 ,  Y10S257/903 ,  Y10S257/904 ,  Y10S257/906

摘要： A static RAM having first word lines each defined by extended gate electrodes of MISFETs constituting memory cells, and second word lines which are separate from the first word lines. The RAM further has a wiring for supplying a fixed potential such as a ground potential to the memory cells, the wiring being formed from the same layer as that for forming the second word lines.

公开(公告)号：US4792841A

公开(公告)日：1988-12-20

申请号：US634037

申请日：1984-07-24

申请人： Kouichi Nagasawa ,  Yoshio Sakai ,  Osamu Minato ,  Toshiaki Masuhara ,  Satoshi Meguro

发明人： Kouichi Nagasawa ,  Yoshio Sakai ,  Osamu Minato ,  Toshiaki Masuhara ,  Satoshi Meguro

IPC分类号： H01L29/78 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8244 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L27/11 ,  H01L29/04

CPC分类号： H01L27/1112 ,  H01L21/28525 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/522 ,  H01L23/53271 ,  H01L2924/0002 ,  Y10S257/903

摘要： Disclosed is an MOSIC including a plurality of silicon gate type MOSFET's in which, after the polycrystalline silicon wirings are formed simultaneously with polycrystalline silicon gates, electrodes contacted with the source and drain regions are made of polycrystalline silicon so as to be connected to the polycrystalline silicon wirings, thereby to prevent the shallow pn junctions of the source and drain regions from being destroyed by the contacts and to provide a high degree of integration to one silicon chip.

摘要翻译： 公开了包括多个硅栅型MOSFET的MOSIC，其中在与多晶硅栅极同时形成多晶硅布线之后，与源极和漏极区域接触的电极由多晶硅制成，以便连接到多晶硅 从而防止源极和漏极区域的浅的pn结被触点破坏并提供与一个硅芯片的高度集成。

公开(公告)号：US4734383A

公开(公告)日：1988-03-29

申请号：US800954

申请日：1985-11-22

申请人： Shuji Ikeda ,  Kouichi Nagasawa ,  Makoto Motoyoshi ,  Kiyoshi Nagai ,  Satoshi Meguro

发明人： Shuji Ikeda ,  Kouichi Nagasawa ,  Makoto Motoyoshi ,  Kiyoshi Nagai ,  Satoshi Meguro

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L21/425

CPC分类号： H01L21/823814 ,  H01L29/0847 ,  H01L27/0928

摘要： After contact holes for the P- and N-type source or drain regions of P- and N-channel MOSFETs have been made at a common step, an N-type impurity is ion-implanted into at least the N-type source or drain regions through the contact holes. The N-type impurity is annealed to form an N-type region which is deeper than the N-type source or drain regions. During the annealing treatment, the N-type source or drain regions are covered with an insulating film.

摘要翻译： 在P和N沟道MOSFET的P型和N型源极区或漏极区的接触孔已经制成了共同的步骤之后，N型杂质被离子注入至少N型源极或漏极 区域通过接触孔。 将N型杂质退火，形成比N型源区或漏区更深的N型区。 在退火处理期间，N型源极或漏极区域被绝缘膜覆盖。

公开(公告)号：US5700704A

公开(公告)日：1997-12-23

申请号：US458615

申请日：1995-06-02

申请人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

发明人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

IPC分类号： H01L27/11 ,  H01L21/8244

CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903 ,  Y10S257/904

摘要： A method is provided for manufacturing a semiconductor integrated circuit device which includes a capacitor element having a first electrode, a second electrode, and a dielectric film formed between said first electrode and said second electrode. In particular, the method includes the step of forming at least one of the first electrode and second electrode with a polycrystalline silicon film which is deposited over a semiconductor substrate by a CVD method and which is doped with an impurity during said deposition to decrease the resistance of the polycrystalline silicon film. The capacitor element formed by this method is particularly useful for memory cells of static random access memory devices.

摘要翻译： 提供一种用于制造半导体集成电路器件的方法，该半导体集成电路器件包括具有形成在所述第一电极和所述第二电极之间的第一电极，第二电极和电介质膜的电容器元件。 特别地，该方法包括用多晶硅膜形成第一电极和第二电极中的至少一个的步骤，该多晶硅膜通过CVD方法沉积在半导体衬底上，并且在所述沉积期间掺杂有杂质以降低电阻 的多晶硅膜。 通过该方法形成的电容器元件对静态随机存取存储器件的存储单元特别有用。

公开(公告)号：US5652457A

公开(公告)日：1997-07-29

申请号：US351173

申请日：1994-11-30

申请人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

发明人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

IPC分类号： H01L27/11 ,  H01L29/76

CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903 ,  Y10S257/904

摘要： Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially.The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines.The source line is formed of a conductive layer identical to that of the word line. The individual data lines of the complementary data line are formed of an identical conductive layer which is different from that of the word line and the source line. The identical conductive layer between the word line and source line and the complementary data line is formed with two word lines: a main word line extended in the first direction identical to that of the word line and source line and used by adopting the divided word line system: and a sub-word line used by adopting the double word line system.

摘要翻译： 这里公开了一种半导体集成电路器件，其包括具有其存储单元的SRAM，SRAM由通过字线控制的转移MISFET和驱动MISFET构成。 驱动MISFET的栅电极和存储单元的转移MISFET的栅电极和字线分别由不同的导电层形成。 驱动MISFET和转移MISFET分别布置成在栅极长度方向上彼此交叉。 字线在驱动MISFET的栅电极的栅极长度方向上延伸，并且部分地与驱动MISFET的栅电极交叉。 存储器单元的两个转移MISFET的各自的栅极电极与彼此间隔开并沿相同方向延伸的两个相应字线连接。 由两个字线限定的区域配置有两个驱动MISFET和源极线。 源极线由与字线的导电层相同的导电层形成。 互补数据线的各个数据线由与字线和源极线不同的导电层形成。 字线和源极线与互补数据线之间的相同的导电层由两条字线形成：主字线在第一方向上延伸，与字线和源极线相同，并通过采用分割字线 系统：采用双字线系统使用的子字线。

公开(公告)号：US5619055A

公开(公告)日：1997-04-08

申请号：US429882

申请日：1995-04-27

申请人： Satoshi Meguro ,  Kiyofumi Uchibori ,  Norio Suzuki ,  Makoto Motoyoshi ,  Atsuyoshi Koike ,  Toshiaki Yamanaka ,  Yoshio Sakai ,  Toru Kaga ,  Naotaka Hashimoto ,  Takashi Hashimoto ,  Shigeru Honjou ,  Osamu Minato

发明人： Satoshi Meguro ,  Kiyofumi Uchibori ,  Norio Suzuki ,  Makoto Motoyoshi ,  Atsuyoshi Koike ,  Toshiaki Yamanaka ,  Yoshio Sakai ,  Toru Kaga ,  Naotaka Hashimoto ,  Takashi Hashimoto ,  Shigeru Honjou ,  Osamu Minato

IPC分类号： H01L21/8244 ,  H01L27/11 ,  H01L29/76

CPC分类号： H01L27/1104 ,  H01L27/11 ,  H01L27/1108 ,  Y10S257/903 ,  Y10S257/904

摘要： A memory cell of the type employing a pair of cross-coupled CMOS inverters of a SRAM is disclosed in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETs. Each load MISFET of a memory cell consists of a source, drain and channel region formed of a semiconductor strip, such as a polycrystalline silicon film strip, and a gate electrode consisting of a different layer conductive film than that of the drive MISFETs. In a memory cell having such a stacked arrangement, the source region and gate electrode of each load MISFET thereof are patterned to have a widely overlapping relationship with each other to form a capacitor element thereacross such that an increase in the overall capacitance associated with each of the memory cell storage nodes is effected thereby decreasing occurrence of soft error. The overlapping relationship for effecting the large capacitor element across the source and gate of the respective load MISFETs is provided by an ion implanting scheme of a p-type impurity into the semiconductor strip. A separate mask for ion-implantation for the formation of the source region of the load MISFET is added followed by the addition of the gate electrode thereof in a manner so as to have a widely overlapping relationship with that of the source region.

摘要翻译： 公开了采用SRAM的一对交叉耦合CMOS反相器的类型的存储单元，其中负载MISFET堆叠在半导体衬底之上和驱动MISFET之上。 存储单元的每个负载MISFET由诸如多晶硅膜条的半导体条形成的源极，漏极和沟道区域以及由不同于导电膜的驱动MISFET组成的栅电极构成。 在具有这种堆叠布置的存储器单元中，每个负载MISFET的源极区域和栅电极被图案化以具有彼此广泛重叠的关系，以形成电容器元件，使得与每个负载MISFET相关联的总体电容的增加 存储单元存储节点被实现，从而减少软错误的发生。 通过p型杂质离子注入到半导体条中的方式来提供跨越各个负载MISFET的源极和栅极的大电容器元件的重叠关系。 添加用于形成负载MISFET的源极区域的离子注入的单独的掩模，然后以与源极区域具有广泛重叠的关系的方式添加其栅电极。

公开(公告)号：US5005068A

公开(公告)日：1991-04-02

申请号：US376953

申请日：1989-07-07

申请人： Shuji Ikeda ,  Katsuro Sasaki ,  Kouichi Nagasawa ,  Satoshi Meguro

发明人： Shuji Ikeda ,  Katsuro Sasaki ,  Kouichi Nagasawa ,  Satoshi Meguro

IPC分类号： H01L21/768 ,  G11C11/41 ,  H01L21/8244 ,  H01L23/522 ,  H01L27/10 ,  H01L27/11

CPC分类号： H01L27/11 ,  H01L27/1112 ,  Y10S257/903 ,  Y10S257/904 ,  Y10S257/906

摘要： A static RAM having first word lines each defined by extended gate electrodes of MISFETs constituting memory cells, and second word lines which are separate from the first word lines. The RAM has a wiring for supplying a fixed potential such as a ground potential to the memory cells, the wiring being formed from the same layer as that for forming the second word lines.

摘要翻译： 一种静态RAM，其具有由构成存储单元的MISFET的扩展栅极电极和由第一字线分开的第二字线构成的第一字线。 RAM具有用于向存储单元提供诸如地电位的固定电位的布线，布线由与用于形成第二字线的层相同的层形成。

公开(公告)号：US06307217B1

公开(公告)日：2001-10-23

申请号：US08181545

申请日：1994-01-14

申请人： Shuji Ikeda ,  Satoshi Meguro ,  Kyoichiro Asayama ,  Eri Fujita ,  Koichiro Ishibashi ,  Toshiro Aoto ,  Sadayuki Morita ,  Atsuyoshi Koike ,  Masayuki Kojima ,  Yasuo Kiguchi ,  Kazuyuki Suko ,  Fumiyuki Kanai ,  Naotaka Hashimoto ,  Toshiaki Yamanaka

发明人： Shuji Ikeda ,  Satoshi Meguro ,  Kyoichiro Asayama ,  Eri Fujita ,  Koichiro Ishibashi ,  Toshiro Aoto ,  Sadayuki Morita ,  Atsuyoshi Koike ,  Masayuki Kojima ,  Yasuo Kiguchi ,  Kazuyuki Suko ,  Fumiyuki Kanai ,  Naotaka Hashimoto ,  Toshiaki Yamanaka

IPC分类号： H01L2972

CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903 ,  Y10S257/904

摘要： A static random access memory comprising memory cells each composed of transfer MISFETs controlled by word lines and of a flip-flop circuit made of driver MISFETs and load MISFETs. The top of the load MISFETs is covered with supply voltage lines so that capacitor elements of a stacked structure are formed between the gate electrodes of the load MISFETs and the supply voltage lines.

摘要翻译： 一种静态随机存取存储器，包括由字线控制的转移MISFET和由驱动器MISFET和负载MISFET构成的触发电路组成的存储单元。 负载MISFET的顶部覆盖有电源电压线，使得层叠结构的电容器元件形成在负载MISFET的栅电极和电源电压线之间。

公开(公告)号：US5483083A

公开(公告)日：1996-01-09

申请号：US028128

申请日：1993-03-09

申请人： Satoshi Meguro ,  Kiyofumi Uchibori ,  Norio Suzuki ,  Makoto Motoyoshi ,  Atsuyoshi Koike ,  Toshiaki Yamanaka ,  Yoshio Sakai ,  Toru Kaga ,  Naotaka Hashimoto ,  Takashi Hashimoto ,  Shigeru Honjou ,  Osamu Minato

发明人： Satoshi Meguro ,  Kiyofumi Uchibori ,  Norio Suzuki ,  Makoto Motoyoshi ,  Atsuyoshi Koike ,  Toshiaki Yamanaka ,  Yoshio Sakai ,  Toru Kaga ,  Naotaka Hashimoto ,  Takashi Hashimoto ,  Shigeru Honjou ,  Osamu Minato

IPC分类号： H01L21/8244 ,  H01L27/11

CPC分类号： H01L27/1104 ,  H01L27/11 ,  H01L27/1108 ,  Y10S257/903 ,  Y10S257/904

摘要： A memory cell of the type employing a pair of cross-coupled CMOS inverters of a SRAM is provided in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETs. Each load MISFET of a memory cell consists of a source, drain and channel region formed of a semiconductor strip, such as a polycrystalline silicon film strip, and a gate electrode consisting of a different layer conductive film than that of the drive MISFETs. A wiring line, formed as a separate conductive layer, is provided in the stacking arrangement of the drive and load MISFETs of a memory cell for applying a ground potential to source regions of the drive MISFETs thereof.

摘要翻译： 提供采用SRAM的一对交叉耦合CMOS反相器的类型的存储单元，其中负载MISFET堆叠在半导体衬底之上和驱动MISFET上方。 存储单元的每个负载MISFET由诸如多晶硅膜条的半导体条形成的源极，漏极和沟道区域以及由与驱动MISFET的不同层导电膜组成的栅电极组成。 在用于将地电位施加到其驱动MISFET的源极区的存储单元的驱动和负载MISFET的堆叠布置中，形成作为单独导电层的布线。