公开(公告)号：US06512245B2

公开(公告)日：2003-01-28

申请号：US09859045

申请日：2001-05-17

申请人： Shuji Ikeda ,  Satoshi Meguro ,  Kyoichiro Asayama ,  Eri Fujita ,  Koichiro Ishibashi ,  Toshiro Aoto ,  Sadayuki Morita ,  Atsuyoshi Koike ,  Masayuki Kojima ,  Yasuo Kiguchi ,  Kazuyuki Suko ,  Fumiyuki Kanai ,  Naotaka Hashimoto ,  Toshiaki Yamanaka

发明人： Shuji Ikeda ,  Satoshi Meguro ,  Kyoichiro Asayama ,  Eri Fujita ,  Koichiro Ishibashi ,  Toshiro Aoto ,  Sadayuki Morita ,  Atsuyoshi Koike ,  Masayuki Kojima ,  Yasuo Kiguchi ,  Kazuyuki Suko ,  Fumiyuki Kanai ,  Naotaka Hashimoto ,  Toshiaki Yamanaka

IPC分类号： H01L2972

CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903 ,  Y10S257/904

摘要： A static random access memory comprising memory cells each composed of transfer MISFETs controlled by word lines and of a flip-flop circuit made of driver MISFETs and load MISFETs. The top of the load MISFETs is covered with supply voltage lines so that capacitor elements of a stacked structure are formed between the gate electrodes of the load MISFETs and the supply voltage lines.

摘要翻译： 一种静态随机存取存储器，包括由字线控制的转移MISFET和由驱动器MISFET和负载MISFET构成的触发电路组成的存储单元。 负载MISFET的顶部覆盖有电源电压线，使得层叠结构的电容器元件形成在负载MISFET的栅电极和电源电压线之间。

公开(公告)号：US06307217B1

公开(公告)日：2001-10-23

申请号：US08181545

申请日：1994-01-14

申请人： Shuji Ikeda ,  Satoshi Meguro ,  Kyoichiro Asayama ,  Eri Fujita ,  Koichiro Ishibashi ,  Toshiro Aoto ,  Sadayuki Morita ,  Atsuyoshi Koike ,  Masayuki Kojima ,  Yasuo Kiguchi ,  Kazuyuki Suko ,  Fumiyuki Kanai ,  Naotaka Hashimoto ,  Toshiaki Yamanaka

发明人： Shuji Ikeda ,  Satoshi Meguro ,  Kyoichiro Asayama ,  Eri Fujita ,  Koichiro Ishibashi ,  Toshiro Aoto ,  Sadayuki Morita ,  Atsuyoshi Koike ,  Masayuki Kojima ,  Yasuo Kiguchi ,  Kazuyuki Suko ,  Fumiyuki Kanai ,  Naotaka Hashimoto ,  Toshiaki Yamanaka

IPC分类号： H01L2972

CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903 ,  Y10S257/904

摘要： A static random access memory comprising memory cells each composed of transfer MISFETs controlled by word lines and of a flip-flop circuit made of driver MISFETs and load MISFETs. The top of the load MISFETs is covered with supply voltage lines so that capacitor elements of a stacked structure are formed between the gate electrodes of the load MISFETs and the supply voltage lines.

摘要翻译： 一种静态随机存取存储器，包括由字线控制的转移MISFET和由驱动器MISFET和负载MISFET构成的触发电路组成的存储单元。 负载MISFET的顶部覆盖有电源电压线，使得层叠结构的电容器元件形成在负载MISFET的栅电极和电源电压线之间。

公开(公告)号：US5264712A

公开(公告)日：1993-11-23

申请号：US881314

申请日：1992-05-07

申请人： Jun Murata ,  Yoshitaka Tadaki ,  Hiroko Kaneko ,  Toshihiro Sekiguchi ,  Hiroyuki Uchiyama ,  Hisashi Nakamura ,  Toshio Maeda ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Ogishima ,  Masaki Nagao ,  Michimasa Funabashi ,  Yasuo Kiguchi ,  Masayuki Kojima ,  Atsuyoshi Koike ,  Hiroyuki Miyazawa ,  Masato Sadaoka ,  Kazuya Kadota ,  Tadashi Chikahara ,  Kazuo Nojiri ,  Yutaka Kobayashi

发明人： Jun Murata ,  Yoshitaka Tadaki ,  Hiroko Kaneko ,  Toshihiro Sekiguchi ,  Hiroyuki Uchiyama ,  Hisashi Nakamura ,  Toshio Maeda ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Ogishima ,  Masaki Nagao ,  Michimasa Funabashi ,  Yasuo Kiguchi ,  Masayuki Kojima ,  Atsuyoshi Koike ,  Hiroyuki Miyazawa ,  Masato Sadaoka ,  Kazuya Kadota ,  Tadashi Chikahara ,  Kazuo Nojiri ,  Yutaka Kobayashi

IPC分类号： H01L21/8234 ,  H01L27/105 ,  H01L21/308 ,  H01L29/66

CPC分类号： H01L27/105 ,  H01L21/823425

摘要： A semiconductor integrated circuit comprising first n-channel MISFETs constituting the memory cells of a storage system, second n-channel MISFETs constituting the peripheral circuits of the storage system, and third n-channel MISFETs constituting the output circuit among the peripheral circuits. The respective threshold voltages of the first n-channel MISFETs, the second n-channel MISFETs and the third n-channel MISFETs are decreased in that order when the respective gate lengths of those MISFETs are substantially the same.

摘要翻译： 一种半导体集成电路，包括构成存储系统的存储单元的第一n沟道MISFET，构成存储系统的外围电路的第二n沟道MISFET和构成外围电路中的输出电路的第三n沟道MISFET。 当这些MISFET的各个栅极长度基本相同时，第一n沟道MISFET，第二n沟道MISFET和第三n沟道MISFET的阈值电压依次减小。

公开(公告)号：US5734188A

公开(公告)日：1998-03-31

申请号：US674185

申请日：1996-07-01

申请人： Jun Murata ,  Yoshitaka Tadaki ,  Hiroko Kaneko ,  Toshihiro Sekiguchi ,  Hiroyuki Uchiyama ,  Hisashi Nakamura ,  Toshio Maeda ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Ogishima ,  Masaki Nagao ,  Michimasa Funabashi ,  Yasuo Kiguchi ,  Masayuki Kojima ,  Atsuyoshi Koike ,  Hiroyuki Miyazawa ,  Masato Sadaoka ,  Kazuya Kadota ,  Tadashi Chikahara ,  Kazuo Nojiri ,  Yutaka Kobayashi

发明人： Jun Murata ,  Yoshitaka Tadaki ,  Hiroko Kaneko ,  Toshihiro Sekiguchi ,  Hiroyuki Uchiyama ,  Hisashi Nakamura ,  Toshio Maeda ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Ogishima ,  Masaki Nagao ,  Michimasa Funabashi ,  Yasuo Kiguchi ,  Masayuki Kojima ,  Atsuyoshi Koike ,  Hiroyuki Miyazawa ,  Masato Sadaoka ,  Kazuya Kadota ,  Tadashi Chikahara ,  Kazuo Nojiri ,  Yutaka Kobayashi

IPC分类号： H01L27/105 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L3/119

CPC分类号： H01L27/105

摘要： A semiconductor integrated circuit comprising first n-channel MISFETs constituting the memory cells of a storage system, second n-channel MISFETs constituting the peripheral circuits of the storage system, and third n-channel MISFETs constituting the output circuit among the peripheral circuits. The respective threshold voltages of the first n-channel MISFETs, the second n-channel MISFETs and the third n-channel MISFETs are decreased in that order when the respective gate lengths of those MISFETs are substantially the same.

公开(公告)号：US5917211A

公开(公告)日：1999-06-29

申请号：US979543

申请日：1997-11-25

申请人： Jun Murata ,  Yoshitaka Tadaki ,  Hiroko Kaneko ,  Toshihiro Sekiguchi ,  Hiroyuki Uchiyama ,  Hisashi Nakamura ,  Toshio Maeda ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Ogishima ,  Masaki Nagao ,  Michimasa Funabashi ,  Yasuo Kiguchi ,  Masayuki Kojima ,  Atsuyoshi Koike ,  Hiroyuki Miyazawa ,  Masato Sadaoka ,  Kazuya Kadota ,  Tadashi Chikahara ,  Kazuo Nojiri ,  Yutaka Kobayashi

发明人： Jun Murata ,  Yoshitaka Tadaki ,  Hiroko Kaneko ,  Toshihiro Sekiguchi ,  Hiroyuki Uchiyama ,  Hisashi Nakamura ,  Toshio Maeda ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Ogishima ,  Masaki Nagao ,  Michimasa Funabashi ,  Yasuo Kiguchi ,  Masayuki Kojima ,  Atsuyoshi Koike ,  Hiroyuki Miyazawa ,  Masato Sadaoka ,  Kazuya Kadota ,  Tadashi Chikahara ,  Kazuo Nojiri ,  Yutaka Kobayashi

IPC分类号： H01L21/8234 ,  H01L27/105 ,  H01L27/08 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L27/105 ,  H01L21/823425

摘要： A semiconductor integrated circuit comprising first n-channel MISFETs constituting the memory cells of a storage system, second n-channel MISFETs constituting the peripheral circuits of the storage system, and third n-channel MISFETs constituting the output circuit among the peripheral circuits. The respective threshold voltages of the first n-channel MISFETs, the second n-channel MISFETs and the third n-channel MISFETs are decreased in that order when the respective gate lengths of those MISFETs are substantially the same.

摘要翻译： 一种半导体集成电路，包括构成存储系统的存储单元的第一n沟道MISFET，构成存储系统的外围电路的第二n沟道MISFET和构成外围电路中的输出电路的第三n沟道MISFET。 当这些MISFET的各个栅极长度基本相同时，第一n沟道MISFET，第二n沟道MISFET和第三n沟道MISFET的阈值电压依次减小。

公开(公告)号：US07098156B2

公开(公告)日：2006-08-29

申请号：US10475142

申请日：2002-04-04

申请人： Takayuki Wakabayashi ,  Toshiyuki Uchino ,  Yasuo Kiguchi ,  Atsuyoshi Koike

发明人： Takayuki Wakabayashi ,  Toshiyuki Uchino ,  Yasuo Kiguchi ,  Atsuyoshi Koike

IPC分类号： H01L21/00

CPC分类号： H01L21/67724 ,  G05B19/41895 ,  H01L21/67173 ,  H01L21/67727 ,  Y02P90/285 ,  Y02P90/60 ,  Y10S414/135

摘要： The conveyance of wafers in bays (equipment groups) of a clean room is performed by RGVs (Rail Guided Vehicles) that linearly travel at high speed on conveying rails laid on the floor of the clean room. A structure is adopted wherein a conveying area, over which the RGV travels, is separated from a human working area by a compartment (partition), and a human is not allowed to enter the conveying area upon operation of a line.

摘要翻译： 在洁净室的托架（设备组）中输送硅片由RGV（轨道导引车辆）执行，该车辆在洁净室地板上的输送轨道上高速线性行进。 采用这样的结构，其中RGV行进的输送区域通过隔室（分隔）与人工作区域分离，并且在操作线路时不允许人进入输送区域。